Mirrored Serial Interface Loopback for SPI Data Integrity

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Solution Overview

Problem

Conventional SPI protocols lack mechanisms for ensuring data sanity, acknowledging receipt of data, and providing flow control, leading to potential errors and inefficiencies in communication between master and slave devices due to the absence of error detection and handshaking signals.

Innovation Solution

A mirrored serial interface (MSI) with a loopback mechanism that loops back data on the MISO and MOSI lines at every clock edge to check for data sanity and presence/absence of devices, and uses multiplexers to switch between data and acknowledgement signals, ensuring data integrity and flow control through single-bit flag and acknowledgement signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional SPI protocol is used for data transfer, then communication between master and slave devices is established, but data sanity cannot be ensured and no acknowledgement mechanism exists to confirm receipt of data

Engineering Contradiction:
Improvedata sanityVSAvoidcommunication protocol
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a loopback mechanism where data transmitted on MOSI line is fed back to the master device through MISO line. The master device compares the transmitted data with the received loopback data at every clock edge to detect errors. This feedback mechanism ensures data sanity and provides automatic error detection without requiring complex external verification systems.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs data sanity checking at every clock edge during the transmission process itself, rather than waiting for complete data transfer. By comparing loopback data with transmitted data continuously, the system proactively detects errors before they propagate, ensuring data integrity throughout the communication process.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If conventional SPI protocol is used, then data transfer occurs, but no flow control mechanism exists to handle slow peripherals

Engineering Contradiction:
Improveflow controlVSAvoidhandshaking signals
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent employs bidirectional data lines (MOSI and MISO) that serve dual purposes: data transmission and flow control. The loopback mechanism provides continuous feedback about the transmission status, enabling the master device to adapt its transmission rate to match the slave device's processing speed, thus providing flow control for slow peripherals.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent makes the existing MOSI and MISO lines multi-functional by using them for both data transmission and flow control/acknowledgement. The loopback mechanism allows the same physical infrastructure to serve multiple purposes, eliminating the need for separate dedicated flow control signal lines.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Loss of information

If conventional SPI protocol is used, then master writes data to slave, but master has no knowledge of whether slave exists or receives data correctly until complete transaction is executed

Engineering Contradiction:
Improvedata receipt confirmationVSAvoidtransaction execution time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The loopback mechanism provides immediate feedback to the master device during each clock cycle. By comparing the transmitted data with the loopback received data in real-time, the master device can instantly detect transmission errors, slave presence, and data integrity issues without waiting for the completion of the entire transaction.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs rapid comparison of loopback data with transmitted data at every clock edge, quickly identifying errors or slave absence. This allows the system to detect and respond to communication issues much faster than waiting for complete transaction execution, effectively 'rushing through' the detection phase.

Inventive Principle:
Principle #21Skipping (Rushing through)

4Reliability

If data is transmitted over serial interface, then communication occurs, but timing violations, channel noise or temperature changes may cause inverted bits

Engineering Contradiction:
Improvedata integrityVSAvoidtiming violations and noise
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The loopback mechanism creates a closed-loop feedback system where the transmitted data is returned to the source. By continuously comparing the original transmitted data with the loopback received data at every clock edge, the system can detect bit inversions caused by timing violations, channel noise, or temperature changes, and identify transmission errors in real-time.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent implements error detection through loopback comparison before the transmission is fully completed. By continuously monitoring data integrity during the transmission process, the system can detect and flag errors early, preventing corrupted data from being fully processed or acted upon.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11567893B2Method and a mirrored serial interface (MSI) for transferring data
Publication Date: 2023.01.31 CENT FOR DEV OF TELEMATICS
  • US11567893B2 patent drawing
  • US11567893B2 patent drawing
  • US11567893B2 patent drawing

AI summary

The present disclosure relates to a mirrored serial interface (MSI) for accessing peripherals through four wire serial interface. More particularly, the present disclosure is related to serial peripheral protocol with looped back mechanism in which contents of source data line are looped back onto the destination line and compared at every clock edge to ensure data sanity and to assert presence of slave and master device during and between cycles.