MIS Capacitor Layout for Leakage Current Cancellation
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Solution Overview
Problem
Integrated MIS capacitors exhibit significant leakage currents in certain applications, leading to inaccurate and unreliable output in high precision circuits due to large equivalent systematic offsets, especially in low quiescent current designs and high precision amplifiers, which are exacerbated by temperature increases.
Innovation Solution
A MIS capacitor design with opposing orientations of p-n junctions within the substrate, where one junction is reverse biased to a supply voltage and the other to a reference voltage, allowing leakage currents to cancel each other out, thereby reducing the net input offset voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional MIS capacitor with a single p-n junction is used, then the capacitor can be integrated into semiconductor circuits, but the leakage current increases exponentially with temperature and introduces significant systematic offsets
Solution Approach 1:
The semiconductor substrate is segmented into three distinct parts with alternating conductivity types (first part: first conductivity type, second part: second conductivity type, third part: first conductivity type). This segmentation creates two separate p-n junctions (first p-n junction between first and second parts, second p-n junction between second and third parts) that can independently generate leakage currents for cancellation purposes
Solution Approach 2:
The patent employs counterbalancing by designing the two p-n junctions to generate equal and opposite leakage currents. The first p-n junction generates a leakage current that is substantially equal in magnitude but opposite in direction to the leakage current from the second p-n junction, causing them to cancel each other out and reduce the net leakage current to a minimal level
2Measurement precision
If the capacitor is designed for high precision applications, then the output accuracy is improved, but the leakage current becomes more significant and unacceptable
Solution Approach 1:
The patent converts the harmful leakage current phenomenon into a beneficial effect by deliberately designing two p-n junctions that generate leakage currents for cancellation. Instead of trying to eliminate leakage current through material improvements alone, the invention uses the leakage current itself as a compensating mechanism, where the harmful leakage from one junction becomes useful when offset by an equal and opposite leakage from the other junction, achieving ultra-low net leakage suitable for high precision applications
3Area of stationary object
If a large area capacitor is used to meet circuit requirements, then the capacitance value is sufficient, but the leakage current increases and creates unacceptable input offset
Solution Approach 1:
The capacitor structure is segmented into three conductivity type regions with two p-n junctions, allowing the large area capacitor to generate two opposing leakage currents that cancel each other. This segmentation enables the capacitor to maintain large area for sufficient capacitance while the opposing leakage currents from the segmented junctions reduce the net leakage and associated input offset voltage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The cancellation of leakage currents results in a substantially zero input offset voltage, independent of temperature variations, enhancing the accuracy and reliability of high precision amplifiers.
Implementation Method 1
The leakage current is may be generated by a PN junction of MIS capacitor. The leakage current may increase exponentially with increasing temperature.
Data Source
AI summary
A MIS capacitor and a method of making the same. The capacitor includes a semiconductor substrate having a first part having a first conductivity type and contact regions for coupling the first part to an output node. The substrate has dielectric on a surface of the first part and electrodes on the dielectric. The substrate has a second part having a second conductivity type and a third part having the first conductivity type. The third part is coupleable to a supply voltage. The second part is located between the first part and the third part. The first part and the second part form a first p-n junction and the second part and the third part form a second p-n junction. A reference contact is provided for coupling the second part to a reference voltage. A further contact region is provided for coupling the second part to the output node.