MIS Contact for 3D Vertical Memory Reducing Dopant Diffusion
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Solution Overview
Problem
As design rules shrink, semiconductor space for fabricating memory devices like DRAM arrays becomes limited, leading to challenges in forming effective contacts that minimize dopant diffusion and contact resistance, while maintaining uniformity and reducing doping requirements.
Innovation Solution
The implementation of a metal insulator semiconductor (MIS) interface between digit lines and source/drain regions, using an insulator material and a conductor material to form a better engineered electrical contact, which reduces dopant diffusion and provides a shared bias to channel regions, improving access device control and refresh performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional direct contact between digit line and source/drain region is used, then fabrication is simpler, but dopant diffusion increases and contact resistance becomes high
Solution Approach 1:
An insulator material layer is introduced between the digit line and source/drain region to serve as an intermediary. This insulator layer prevents direct contact that would cause dopant diffusion, while still allowing electrical contact through the metal-insulator-semiconductor (MIS) interface, thereby reducing contact resistance without increasing dopant diffusion.
Solution Approach 2:
The contact structure uses a composite arrangement of conductor material (digit line), insulator material (interface layer), and semiconductor material (source/drain region). This composite structure combines the benefits of electrical conductivity from the metal with the protective insulation properties, achieving low contact resistance while preventing dopant diffusion.
2Reliability
If high source/drain doping is used, then contact resistance decreases, but dopant diffusion increases and device uniformity deteriorates
Solution Approach 1:
The insulator material acts as a barrier that prevents dopant diffusion from the source/drain region into the digit line and surrounding areas. This allows the use of optimized doping levels without excessive diffusion, maintaining device uniformity while achieving acceptable contact resistance through the MIS interface mechanism.
3Productivity
If design rules are shrunk to increase memory capacity, then device density increases, but contact formation becomes more difficult and dopant diffusion control becomes harder
Solution Approach 1:
The insulator material layer provides a defined interface that simplifies contact formation in scaled devices. By establishing a clear MIS interface structure, the contact formation process becomes more controllable even at smaller dimensions, preventing excessive dopant diffusion that would be problematic in miniaturized devices.
Solution Approach 2:
The introduction of the insulator material changes the physical and electrical parameters of the contact interface. This parameter change enables better control over dopant diffusion and contact resistance in scaled devices, allowing memory density to increase while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more uniform and lower resistance contacts, reducing the need for high source/drain doping and enhancing the performance of memory devices by improving access device control and refresh capabilities.
Implementation Method 1
an insulator material and a conductor material are formed on a surface of the first source/drain region to form a metal insulator semiconductor (MIS) interface
Implementation Method 2
reduces dopant diffusion
Implementation Method 3
provides a shared bias to channel regions, improving access device control and refresh performance
Data Source
AI summary
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. In one example, an insulator material is formed on a surface of the first source/drain region and a conductor material formed on the insulator material to form a metal insulator semiconductor (MIS) interface between the horizontally oriented digit lines and the first source/drain regions of the horizontally oriented access devices.