MIS Contact Structures for CMOS Transistors
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Solution Overview
Problem
The formation of metal silicide regions in advanced transistor devices, such as those using silicon germanium or III-V materials, faces challenges like increased contact resistance, non-continuous layers, agglomeration, and electrical shorts due to the limitations of traditional metal silicide formation techniques, particularly in reduced-size contact openings and non-traditional substrate materials.
Innovation Solution
The method involves forming MIS contact structures through conformal deposition of layers including a contact insulating material, a metal-containing layer, and a conductive cap layer, followed by contact ion implantation and subsequent processing to define the contact structures, allowing for tailored material selection and improved contact formation in CMOS applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional metal silicide formation techniques are used in reduced-size contact openings, then contact resistance is reduced, but non-continuous layers and agglomeration occur
Solution Approach 1:
The patent changes the material parameters by replacing traditional metal silicide with MIS contact structures consisting of metal layer, insulator layer, and semiconductor layer. This parameter change in material composition and structure enables continuous layer formation in reduced-size contact openings while maintaining low contact resistance, resolving the contradiction between reliability and manufacturing precision.
2Reliability
If additional heating processes are performed to convert metal silicide to lower resistance phase, then contact resistance is reduced, but thermal budget is reduced and non-continuous layers form
Solution Approach 1:
The patent changes the material system from metal silicide requiring thermal processing to MIS contact structures that achieve low contact resistance through material selection and conformal deposition without additional heating processes. This eliminates the thermal budget consumption while maintaining low contact resistance and ensuring layer continuity.
3Adaptability or versatility
If metal silicide regions are formed in non-traditional substrate materials like silicon germanium or III-V materials, then device compatibility is improved, but contact resistance increases
Solution Approach 1:
The patent employs composite MIS contact structures with specifically selected metal, insulator, and semiconductor layers that are compatible with non-traditional substrate materials like silicon germanium and III-V materials. The composite structure achieves low contact resistance on these materials while maintaining device compatibility, resolving the contradiction between adaptability and reliability.
4Productivity
If contact openings are reduced in size to increase packing density, then chip area efficiency is improved, but metal silicide formation becomes difficult and agglomeration occurs
Solution Approach 1:
The patent changes the contact structure parameters from traditional metal silicide to MIS contact structures that can be formed through conformal deposition processes. This enables precise formation in reduced-size contact openings without agglomeration, achieving high packing density while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency and effectiveness of MIS contact structure formation, reducing contact resistance and preventing issues like agglomeration and electrical shorts, thereby improving the performance and reliability of transistor devices in high packing density applications.
Implementation Method 1
performing a contact ion implantation process through the implant masking layer to form a contact ion implant region comprising a contact ion that is positioned at least partially in at least one of the first, second or third layers of material positioned within the second contact opening
Data Source
AI summary
A method that includes, among other things, forming first and second contact openings in a layer of insulating material that respectively expose a portion of first and second source/drain (S/D) regions of first and second transistors that are of the opposite type, forming first, second and third layers of material within each of the first and second contact openings, and forming an implant masking layer that masks the first contact opening while leaving the second contact opening exposed for further processing. The method also includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, removing the implant masking layer and forming a conductive material in both the first and second contact openings so as to define first and second MIS contact structures positioned in the first and second contact openings.