MIS Edge Structure for Micro LEDs With Lower Leakage

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The reduction in size of optoelectronic devices, such as LEDs, leads to performance issues like higher leakage current, charge crowding, and non-radiative recombination due to defects and material limitations, which affect the efficiency and functionality of micro devices.

Innovation Solution

The implementation of a Metal-Insulator-Semiconductor (MIS) structure on the edges of micro devices, with a dielectric layer and a conductive gate, along with extended micro device contacts, to modulate the internal electrical field and control lateral current flow, thereby reducing leakage and improving charge balance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the size of optoelectronic devices is reduced to create higher pixel density, then device density and functionality are improved, but device performance deteriorates due to higher leakage current, charge crowding, and non-radiative recombination

Engineering Contradiction:
Improvepixel densityVSAvoiddevice performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies different properties to different regions of the device by implementing MIS structures specifically at the edges and perimeters of micro devices. This local modification creates high-resistance regions that selectively suppress leakage current at critical areas without affecting the overall device functionality, thereby maintaining high pixel density while improving device performance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the electrical parameters of the device by introducing MIS structures that modify the resistance characteristics at device edges. The metal-insulator-semiconductor structures create localized high-resistance regions that alter current flow patterns, reducing leakage current and charge crowding effects while maintaining the reduced device size for high pixel density.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If MIS structures are implemented on device edges to reduce leakage current, then device performance is improved, but device complexity increases

Engineering Contradiction:
Improvedevice performanceVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the device structure by implementing MIS structures only at specific edge regions rather than uniformly across the entire device. This segmentation approach applies the complexity-only where needed (at perimeters and edges where leakage occurs), leaving the central active regions simple and unchanged, thereby improving performance while minimizing overall structural complexity.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the performance of micro devices by minimizing lateral current flow, reducing defects, and maintaining device efficiency, allowing for higher pixel density and brightness in LED displays while reducing fabrication costs.

Implementation Method 1

at least part of an edge of a micro device is covered with a metal-insulator-semiconductor (MIS) structure, wherein the MIS structure comprises a MIS dielectric layer and a MIS gate

Methodology Applied
Scientific EffectMetal-Insulator-Semiconductor structure:

Data Source

PatentUS20240379897A1High efficent micro devices
Publication Date: 2024.11.14 VUEREAL INC
  • US20240379897A1 patent drawing
  • US20240379897A1 patent drawing
  • US20240379897A1 patent drawing

AI summary

A micro device structure comprising at least part of an edge of a micro device is covered with a metal-insulator-semiconductor (MIS) structure, wherein the MIS structure comprises a MIS dielectric layer and a MIS gate conductive layer, at least one gate pad provided to the MIS gate conductive layer, and at least one micro device contact extended upwardly on a top surface of the micro device.