Vertical MIS Microdevice Sidewall Defect Suppression
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Solution Overview
Problem
Sidewall defects in microdevices lead to performance degradation, and the use of additional electrodes in small devices poses a challenge.
Innovation Solution
The gate of the MIS structure is shorted to either the n-contact or p-contact, with a bias voltage engineered to be close to zero or greater than zero, enhancing the external quantum efficiency (EQE) and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate electrode is added around the device to deactivate sidewall defects, then device performance is improved, but device complexity increases due to extra electrodes in a small device
Solution Approach 1:
The gate electrode is merged with an existing contact structure (n-contact or p-contact) by shorting them together. This eliminates the need for a separate gate electrode while still providing the necessary electric field to deactivate sidewall defects and improve device performance.
Solution Approach 2:
The contact structure serves dual functions: it provides electrical connection and simultaneously acts as the gate electrode to control sidewall defects. This multi-functionality reduces the number of components needed in the microdevice.
2Productivity
If the gate is shorted to n-contact to provide zero bias difference, then external quantum efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate and n-contact are electrically merged through shorting, ensuring zero bias difference between them. This simplifies the biasing scheme and improves external quantum efficiency by eliminating leakage current, while the manufacturing precision challenge is addressed through standard semiconductor fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases EQE and reduces sensitivity to electrostatic discharge (ESD), while maintaining efficiency and functionality in vertical solid state devices.
Implementation Method 1
side walls comprising a metal-insulator-semiconductor (MIS) structure, wherein gate of the MIS structure is shorted at least one contact of the vertical solid state device
Implementation Method 2
use a gate around the device to deactivate the defects by biasing the gate
Data Source
AI summary
A vertical solid state device comprising: a connection pad; and side walls comprising a metal-insulator-semiconductor (MIS) structure; wherein a gate of the MIS structure is shorted to at least one contact of the vertical solid state device and a threshold voltage (VT) of the MIS structure is adjusted to increase the efficiency of the device.