MIS QFN Substrate With DC Blocking Capacitors for High-Speed Channels
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Solution Overview
Problem
High-speed signal/data devices, such as re-timer circuits and clock synthesizers, face high costs due to the poor electrical performance of wirebond BGA packages at speeds above 5 Gbps, which is not adequately addressed by conventional packaging technologies.
Innovation Solution
A molded interconnect substrate (MIS) QFN technology is developed with narrowed signal traces and in-package DC blocking capacitors, featuring a bottom metal layer with ground cuts, to provide a cost-effective solution that matches the performance of conventional FC BGA packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wirebond BGA package is used, then manufacturing cost is reduced, but electrical performance at high speed deteriorates
Solution Approach 1:
The patent applies parameter changes by modifying the trace geometry parameters (narrowing the trace width) and adding DC blocking capacitors to the wirebond BGA package structure. These parameter changes enable the package to achieve high-speed electrical performance (56 Gbps+) that was previously only available in expensive FC BGA packages, while maintaining the cost advantages of wirebond technology.
2Reliability
If FC BGA package is used, then electrical performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent employs the principle of using cheaper components (wirebond BGA package structure) and enhancing them with specific modifications (narrowed traces, DC blocking capacitors, ground cuts) to achieve performance previously requiring expensive FC BGA packages. This substitution of cheaper components with performance-enhancing features directly addresses the cost-performance contradiction.
3Reliability
If FC BGA package is used, then electrical performance is improved, but production time increases
Solution Approach 1:
The patent substitutes the expensive, time-consuming FC BGA package process with a modified wirebond BGA package structure that incorporates performance-enhancing features. The wirebond process itself is faster and more suitable for high-volume production, and the additional features (narrowed traces, capacitors, ground cuts) are integrated into this faster manufacturing flow, thereby reducing production time while maintaining high electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MIS QFN technology achieves similar performance to conventional FC BGA packages while reducing costs by 40-60% and shortening production cycles, meeting specifications for insertion loss and return loss at high data rates like 56 Gbps.
Implementation Method 1
DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling
Data Source
AI summary
A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.