Vertical MIS Structure Oxidation for Dielectric Isolation
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Solution Overview
Problem
In semiconductor devices with buried gate electrode structures, achieving desired dielectric isolation while avoiding the complexities and reliability issues associated with forming dielectric materials, such as reduced electric strength and increased process complexity, is a challenge.
Innovation Solution
The method involves increasing the oxidation rate of exposed surface portions of electrode materials during an oxidation process, using techniques like incorporating arsenic dopant species or inducing crystal damage, to form oxide layers with significantly different thicknesses, thereby enhancing dielectric breakdown voltage and dynamic behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric materials are formed to provide isolation between electrode structures, then electrical insulation is improved, but process complexity increases and electric strength is reduced
Solution Approach 1:
The electrode structures themselves serve the dual function of providing both electrical conduction and electrical insulation through their oxidized surfaces. The oxide layers formed on the electrode surfaces provide the dielectric isolation, eliminating the need for separate dielectric material formation processes.
Solution Approach 2:
The oxidation state and oxide layer thickness of the electrode surfaces are controlled as key parameters. By adjusting oxidation conditions and selective oxidation rates, the patent achieves proper electrical insulation between structures while maintaining the conductive function of the electrodes themselves.
2Reliability
If oxide layers are formed between electrode structures, then dielectric isolation is improved, but capacitive coupling increases
Solution Approach 1:
Selective oxidation is applied to specific surfaces of electrode structures based on their spatial location and functional requirements. Different oxide layer thicknesses are formed on different surfaces - thicker oxides where isolation is critical and thinner oxides where capacitive coupling must be minimized, achieving local optimization of electrical properties.
3Strength
If oxidation rate is increased to form thicker oxide layers, then dielectric strength is improved, but oxidation process control becomes more difficult
Solution Approach 1:
Different regions of the electrode structures are selectively oxidized at different rates to form oxide layers with locally optimized thicknesses. This selective approach allows thicker oxide layers (for higher dielectric strength) in isolation-critical regions while maintaining thinner oxide layers (for better process control) in other regions.
Solution Approach 2:
The oxidation process parameters (temperature, time, atmosphere composition) are optimized to achieve the desired oxide thickness and quality. By carefully controlling these parameters, the patent forms sufficiently thick oxide layers for dielectric strength while maintaining oxidation process control and repeatability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves dielectric strength and dynamic performance by forming oxide layers with increased thickness, reducing capacitive coupling and enhancing reliability, while maintaining process control and efficiency.
Implementation Method 1
concurrently oxidizing the exposed surface of the crystalline semiconductor region in the cavity and an exposed surface of the first semiconductor electrode so as to form a first oxide layer on the exposed surface of the crystalline semiconductor region and a second oxide layer on the exposed surface of the first semiconductor electrode
Data Source
Figure 1a
Figure 1b~1c
Figure 1d~1e
AI summary
A method of forming an MIS (metal-insulator-semiconductor) structure, the method comprising: forming a first semiconductor electrode in a cavity formed in a crystalline semiconductor region by depositing a first silicon containing layer provided with an increased oxidation rate relatively to an exposed surface of said crystalline semiconductor region in said cavity and depositing a second silicon containing layer above said silicon containing layer with a different oxidation rate relatively to said silicon containing layer, said first semiconductor electrode being electrically insulated from said crystalline semiconductor region by an insulating layer, concurrently oxidizing said exposed surface of said crystalline semiconductor region in said cavity and an exposed surface of said first semiconductor electrode so as to form a first oxide layer on said exposed surface of said first semiconductor electrode and a second oxide layer on said exposed surface of said crystalline semiconductor region and forming a second semiconductor electrode in said cavity and above said first semiconductor electrode, said second semiconductor electrode being electrically isolated from said first semiconductor electrode by said first oxide layer.