MIS Transistor Gate Electrode Work Function Control
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Solution Overview
Problem
The production of semiconductor devices with high-performance MOSFETs and CMOSFETs faces challenges such as increased gate parasitic resistance, decreased effective capacitance of insulating films, and variations in threshold voltage due to carrier depletion and impurity spreading, which complicates the manufacturing process and increases costs.
Innovation Solution
A semiconductor device with a stack structure of a metal layer and a compound layer, where the metal layer has a work function of 4.3 eV or smaller, and the compound layer contains a IV-group semiconductor, is used for n-channel and p-channel MIS transistors, along with a method involving heat treatment to form compound layers and control the work function, reducing the complexity of the production process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If different metal elements are added to control work function for different conductivity types, then optimal threshold voltage is achieved, but production process complexity increases
Solution Approach 1:
The patent applies local quality by forming different metal layer compositions selectively for n-type and p-type transistors. A first metal layer with a first composition is formed for n-type transistors to achieve a first work function, while a second metal layer with a second composition is formed for p-type transistors to achieve a second work function. This allows optimal threshold voltage control for each transistor type while maintaining a unified process framework.
2Manufacturing precision
If different metal elements are added to control work function for different conductivity types, then optimal threshold voltage is achieved, but production costs increase
Solution Approach 1:
The patent merges the work function control process into a single unified process step. Both the first metal layer for n-type transistors and the second metal layer for p-type transistors are formed simultaneously in one process, rather than requiring separate processing steps for each transistor type. This consolidation reduces production complexity and costs while achieving the required threshold voltage control.
3Manufacturing precision
If Al is deposited simultaneously with Ni to form fully-silicided gate electrode, then work function of 4.3 eV is achieved for n-type MOS, but Al enters crystal grain boundary causing in-plane variation
Solution Approach 1:
The patent segments the metal layer formation process by using separate metal layers with different compositions for n-type and p-type transistors instead of mixing multiple metal elements in a single layer. This segmentation prevents harmful intermixing and diffusion of metal elements that would occur in a fully-silicided structure with multiple metals deposited simultaneously, thereby maintaining uniform dielectric properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower leakage current and optimal threshold values for the semiconductor devices, simplifying the production process and reducing costs by allowing for the use of a single silicide phase for both conductivity types.
Implementation Method 1
a first gate electrode having a stack structure formed with a first metal layer and a first compound layer, the first metal layer being formed on the first gate insulating film and being made of a first metal having a work function of 4.3 eV or smaller
Implementation Method 2
a method involving heat treatment to form compound layers and control the work function
Data Source
AI summary
A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.