MIS Transistor Memory Cell with Doped Substrate for Impact Ionization Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile memory circuits utilizing hot-carrier effects for data storage face issues with impact ionization, which can lead to improper circuit function and reduced circuit density due to the need for additional contacts to manage substrate potentials.
Innovation Solution
A memory circuit design incorporating a MIS transistor with a highly-doped substrate layer and lightly-doped diffusion regions, where the gate electrode and sidewalls create a lingering change in transistor characteristics through a hot-carrier effect, reducing the threshold voltage and suppressing impact ionization effects by controlling the gate and source/drain nodes with a control circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hot-carrier effect is utilized for data storage in MIS transistor, then nonvolatile memory function is achieved, but impact ionization occurs causing improper circuit function
Solution Approach 1:
The substrate is divided into two regions with different doping characteristics: a first substrate region with high doping concentration and a second substrate region with low doping concentration. This local differentiation allows the high-doping region to suppress impact ionization while the low-doping region maintains the hot-carrier effect for data storage, thus resolving the contradiction between reliability and harmful factors.
2Reliability
If additional contacts are added to manage substrate potentials, then impact ionization is suppressed, but circuit density is reduced
Solution Approach 1:
The substrate potential control function is merged into the substrate structure itself through doping concentration differentiation, rather than requiring separate control contacts. The high-doping region inherently provides low resistance and potential stabilization, eliminating the need for additional contacts and maintaining high circuit density while ensuring reliable substrate potential control.
3Ease of manufacture
If MIS transistor structure is used for nonvolatile memory, then cost is reduced compared to special structures, but impact ionization adverse effects occur
Solution Approach 1:
By creating local quality differences in the substrate through selective doping, the patent enables the simple MIS transistor structure to suppress impact ionization without requiring complex additional structures like floating gates or special materials. This maintains manufacturing simplicity and cost-effectiveness while eliminating the harmful impact ionization effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively suppresses the adverse effects of impact ionization, ensuring proper circuit operation and increasing circuit density by eliminating the need for contacts near diffusion regions, thus enhancing data retention and storage capabilities.
Implementation Method 1
The MIS transistor used as a nonvolatile memory cell in PermSRAM is configured to experience an irreversible hot-carrier effect on purpose for storage of one-bit data. Here, the irreversible hot-carrier effect refers to the injection of electrons into the oxide film and/or sidewalls.
Implementation Method 2
Since PermSRAM actively utilizes hot carriers having high-kinetic energy, impact ionization is likely to occur. In general, an electron having enough kinetic energy in a semiconductor material can knock a bound electron out of its bound state to create an electron-hole pair.
Implementation Method 3
The irreversible hot-carrier effect refers to the injection of electrons into the oxide film and/or sidewalls. A change in the transistor characteristics caused by a hot-carrier effect represents one-bit data '0' or '1'.
Data Source
AI summary
A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor in a first operation such that a lingering change is created in transistor characteristics of the MIS transistor in response to the data stored in the latch, wherein the MIS transistor includes a highly-doped substrate layer, a lightly-doped substrate layer disposed on the highly-doped substrate layer, diffusion regions formed in the lightly-doped substrate layer, a gate electrode, sidewalls, and an insulating film.