MIS Transistor Sidewall Carrier Trapping for Nonvolatile Memory
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Solution Overview
Problem
There is a need for a nonvolatile memory circuit that effectively induces carrier trapping in the sidewalls of MIS transistors to enhance data retention, as carriers trapped in sidewalls are more sustainable than those in the insulating film, and existing PermSRAM technologies do not adequately achieve this.
Innovation Solution
The memory circuit includes a latch and a MIS transistor with diffusion regions under the gate electrode and sidewalls, where the metallurgical junction of each diffusion region is positioned under the gate, and a lateral boundary of the depletion layer serves as a drain, facilitating hot carrier injection into the sidewalls for a stable and sustainable change in threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If carriers are trapped in the insulating film for data retention, then data storage is achieved, but the retention duration is limited compared to sidewall trapping
Solution Approach 1:
The patent applies local quality by creating different functional regions within the transistor structure. The sidewalls are specifically engineered with particular doping concentrations and geometries to preferentially trap carriers, while the insulating film serves a different function. This spatial differentiation of properties ensures that carriers are directed to and retained in the sidewalls, achieving superior data retention compared to uniform structures that rely solely on insulating film trapping.
Solution Approach 2:
The patent transitions from two-dimensional carrier trapping in the insulating film to three-dimensional trapping in the sidewalls. By utilizing the vertical dimension and creating depletion regions that extend into the sidewall structures, the patent provides additional carrier confinement pathways. This dimensional expansion significantly enhances carrier retention sustainability and data storage reliability.
2Ease of manufacture
If the MIS transistor uses conventional structure without special materials, then manufacturing cost is reduced, but carrier trapping efficiency in sidewalls is insufficient
Solution Approach 1:
The patent employs parameter changes by optimizing doping concentrations, junction depths, and sidewall geometries to achieve effective carrier trapping without introducing special materials. By carefully controlling these physical parameters during manufacturing, the patent enables conventional fabrication processes to produce transistors with enhanced sidewall trapping capability, thus maintaining cost-effectiveness while improving precision.
3Ease of manufacture
If the metallurgical junction is positioned away from under the gate, then manufacturing is simplified, but transistor characteristics become unstable against manufacturing variations
Solution Approach 1:
The patent applies preliminary action by pre-positioning the metallurgical junction under the gate electrode during the fabrication process. This intentional placement, performed as a deliberate step in the manufacturing sequence, ensures that the junction is correctly positioned before subsequent processing steps. This preliminary positioning action stabilizes transistor characteristics against manufacturing variations while maintaining ease of manufacture through standardized fabrication procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures stable transistor characteristics against manufacturing variations and achieves a large, sustainable change in transistor characteristics, enabling effective nonvolatile data retention by preferentially trapping carriers in the sidewalls.
Implementation Method 1
the MIS transistor used as a nonvolatile memory cell experiences an irreversible hot-carrier effect on purpose for storage of one-bit data. Here, the irreversible hot-carrier effect refers to the injection of carriers into the insulating film (i.e., oxide film) and/or sidewalls, which causes a change in the transistor's threshold voltage.
Implementation Method 2
hot electrons having high-kinetic energy flowing through a transistor channel from the source to the drain cause impact ionization to occur at the channel/drain junction to create electron-hole pairs
Data Source
AI summary
A memory circuit includes a latch having a first node and a second node, a MIS transistor having a gate node, a first source/drain node coupled to the first node of the latch, and a second source/drain node, and a control circuit configured to control the gate node and second source/drain node to make a lingering change in a threshold voltage of the MIS transistor in a first operation and to cause the latch in a second operation to store data responsive to whether a lingering change in the threshold voltage is present, wherein the MIS transistor includes diffusion regions, a gate electrode, and sidewalls, wherein a metallurgical junction of each of the diffusion regions is positioned under the gate electrode, and a lateral boundary of a depletion layer in the diffusion region serving as a drain is positioned under a corresponding one of the sidewalls in the first operation.