Selective Stressor Film for MIS Transistor Drivability

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional semiconductor devices with stress insulating films on gate electrodes suffer from deteriorated drivability due to directional stress orientations that do not align with optimal stress requirements for both gate length and width directions in MIS transistors, leading to compromised performance in N-type and P-type MOS transistors.

Innovation Solution

The semiconductor device design includes a stress insulating film on the upper face and side faces facing the gate length direction of the gate electrode, while omitting coverage on side faces facing the gate width direction, allowing specific stress orientations to improve drivability by applying compressive or tensile stress only in the gate length direction, thereby enhancing transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a stress insulating film is provided on all side faces of the gate electrode including those facing the gate width direction, then stress is applied to the channel in both gate length and gate width directions, but the drivability of the MIS transistor deteriorates due to inappropriate stress orientation in the gate width direction

Engineering Contradiction:
Improvechannel stress applicationVSAvoidtransistor drivability
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The patent applies different stress conditions to different regions of the gate electrode. The stress insulating film is selectively formed only on side faces facing the gate length direction, while omitting coverage on side faces facing the gate width direction. This local differentiation ensures that stress is applied only where it improves drivability (gate length direction) and avoided where it causes deterioration (gate width direction), resolving the contradiction between stress application and transistor performance.

Inventive Principle:
Principle #3Local quality

2Ease of operation

If the stress insulating film covers the gate electrode in the gate length direction, then tensile or compressive stress improves drivability, but covering the gate width direction causes detrimental stress that compromises performance

Engineering Contradiction:
Improvetransistor drivabilityVSAvoiddetrimental stress orientation
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent segments the gate electrode side faces into two distinct groups: those facing the gate length direction and those facing the gate width direction. The stress insulating film is applied only to the first group while deliberately omitting the second group. This segmentation allows beneficial stress to be applied in the gate length direction while avoiding harmful stress in the gate width direction, thus resolving the contradiction between improving drivability and avoiding detrimental effects.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration prevents deterioration in drivability by ensuring appropriate stress orientations in the gate length direction while avoiding detrimental stress in the gate width direction, resulting in improved performance for both N-type and P-type MIS transistors.

Implementation Method 1

a first stressor insulating film provided on an upper face and side faces facing in a gate length direction of the first gate electrode such that first stress acts on a channel of the first MIS transistor in the gate length direction

Methodology Applied
Scientific EffectStress (tensile/compressive): Tension

Data Source

PatentUS7812374B2Semiconductor device and fabrication method thereof
Publication Date: 2010.10.12 GODO KAISHA IP BRIDGE 1
  • US7812374B2 patent drawing
  • US7812374B2 patent drawing
  • US7812374B2 patent drawing

AI summary

A semiconductor device includes a first MIS transistor on a first active region of a semiconductor substrate, the first MIS transistor including: a first gate insulating film provided on the first active region; a first gate electrode provided on the first gate insulating film; a first stressor insulating film provided on an upper face and side faces facing in a gate length direction of the first gate electrode such that first stress acts on a channel of the first MIS transistor in the gate length direction; and a first base insulating film provided on side faces of the first gate electrode facing in a gate width direction, wherein the side faces of the first gate electrode facing in the gate width direction are not covered with the first stressor insulating film.