MISFET Overlap Region Relieves Electric Field Concentration
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Solution Overview
Problem
In semiconductor devices, particularly high-voltage MOSFETs, the miniaturization is hindered by the need to elongate the offset length of the lightly doped drain (LDD) structure to mitigate hot carriers, which increases the length of the low-concentration region and affects device performance.
Innovation Solution
A semiconductor device with a MISFET structure that includes a low-concentration region and a high-concentration region with partial overlap of the well region, reducing electric field concentration at the end of the low-concentration region without elongating the offset length, thereby promoting miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the offset length of the LDD structure is elongated to mitigate hot carriers, then hot carrier effects are suppressed, but the device size increases and miniaturization is hindered
Solution Approach 1:
The patent applies local quality by creating a region where the well and low-concentration region overlap, forming a localized area with modified electrical characteristics. This overlap region has different impurity concentration distribution compared to conventional structures, providing localized electric field relief at the drain end without extending the overall offset length, thus suppressing hot carriers while maintaining compact device dimensions.
2Reliability
If the low-concentration region length is increased to reduce electric field concentration, then hot carrier generation is reduced, but the device area increases
Solution Approach 1:
The patent utilizes another dimension by introducing vertical overlap between the well region and low-concentration region in the cross-sectional direction. This three-dimensional configuration allows the low-concentration region to provide electric field relief through vertical positioning rather than horizontal extension, thereby relieving electric field concentration without increasing the planar device area and enabling continued miniaturization.
Data Source
AI summary
Provided is a technique for promoting miniaturization of a MISFET. A p-type well region is disposed between LDDs (n-type low-concentration regions) of a MISFET (Qn) to cause both the well region and the low-concentration region to partially overlap each other, whereby an overlap region formed of an n-type semiconductor region having a higher resistance than that of the n-type low-concentration region is provided between the p-type well region and each of the n-type low-concentration regions. In this way, the overlap region can relieve an electric field concentration at the end of the n-type low-concentration region, thereby suppressing the occurrence of hot carriers without elongating an offset length of the LDD, which can promote the miniaturization of the MISFET (Qn), particularly, that operates at high voltage.