MISFET Gate and Wire Non-Overlap Layout for Plug Resistance
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Solution Overview
Problem
The miniaturization of LCD drivers leads to high resistance issues in plugs connecting high voltage resistant MISFETs and wires due to increased aspect ratios, while attempts to reduce plug diameter result in voltage resistance failures between gate electrodes and wires.
Innovation Solution
The semiconductor device design features a gate electrode and source/drain wires arranged such that they are not planarly overlapped, with the wires formed on the interlayer insulation film of the first layer, reducing the aspect ratio of plugs and maintaining voltage resistance by increasing the distance between wires and gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the plug diameter is reduced to achieve miniaturization, then the device size is reduced, but the plug resistance increases due to increased aspect ratio
Solution Approach 1:
The patent positions wires on the interlayer insulation film of the first layer rather than the second layer, changing the vertical dimension arrangement. This dimensional repositioning reduces the plug aspect ratio by shortening the penetration depth, thereby reducing plug resistance while maintaining miniaturization benefits.
Solution Approach 2:
The patent introduces an intermediary structure (interlayer insulation film of the first layer) between the plug and the gate electrode. By positioning wires on this intermediary layer, the patent creates optimal spacing that reduces capacitive coupling and plug resistance without increasing device footprint.
2Area of stationary object
If wires are positioned closer to reduce device area, then area is reduced, but voltage resistance failures occur between gate electrodes and wires
Solution Approach 1:
The patent utilizes the vertical dimension by positioning wires on the interlayer insulation film of the first layer, creating sufficient vertical separation between wires and gate electrodes. This dimensional arrangement maintains voltage resistance while optimizing horizontal area utilization.
Solution Approach 2:
The patent creates an asymmetric vertical arrangement where wires on the first layer are positioned at different heights relative to gate electrodes. This asymmetric positioning optimizes both area utilization and voltage resistance by preventing direct alignment between wires and gate electrodes in the vertical dimension.
3Reliability
If plugs penetrate multiple interlayer insulation films, then connection is achieved, but aspect ratio increases and manufacturing complexity increases
Solution Approach 1:
The patent extracts the wire connection from the second interlayer insulation film and relocates it to the first interlayer insulation film. This extraction simplifies the plug structure by reducing the number of layers the plug must penetrate, thereby reducing aspect ratio and manufacturing complexity while maintaining connection reliability.
Data Source
AI summary
In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.