Self-Aligned III-V Nitride MISHEMT Electrodes Using Single Mask
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Solution Overview
Problem
Current GaN/AlGaN HEMT fabrication processes face challenges such as the need for gold-based materials, lack of a common metal stack for source, drain, and gate electrodes, and the complexity of self-aligned processes, which are not CMOS compatible and require multiple masks.
Innovation Solution
A method for fabricating high electron mobility transistors using a gold-free CMOS compatible common metal stack for source, drain, and gate electrodes with a single lithographic mask, employing a Ti/Al/NiV metal layering and low-temperature annealing, allowing for self-aligned formation of ohmic contacts and flexible processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gold-based materials are used for source, drain and gate electrodes, then good contact properties are achieved, but CMOS compatibility is lost and cost increases
Solution Approach 1:
The patent changes the material parameters by replacing gold-based metals with non-gold based metals (such as Ti/Al/NiV stacks) that achieve comparable contact properties while being CMOS compatible. This parameter change in material composition resolves the contradiction between good contact properties and CMOS compatibility.
Solution Approach 2:
The patent employs standard non-gold based metal stacks that are cheaper and more compatible with CMOS processes, sacrificing the superior but expensive gold-based contact properties for broader adaptability and cost-effectiveness in commercial CMOS fabrication.
2Reliability
If separate metal stacks are used for source, drain and gate electrodes, then optimized performance for each electrode is achieved, but process complexity increases and alignment precision is compromised
Solution Approach 1:
The patent merges the formation of source, drain and gate metal stacks into a single common metal stack that is deposited simultaneously. This combining approach reduces process complexity and eliminates multiple alignment steps while maintaining optimized performance for each electrode through selective etching and patterning.
Solution Approach 2:
The common metal stack serves multiple functions as source, drain and gate electrodes simultaneously. This universal metal stack structure eliminates the need for separate metal deposition processes for each electrode, reducing overall process complexity while maintaining the ability to optimize each electrode's performance through subsequent selective processing.
3Manufacturing precision
If multiple lithographic masks are used for source, drain and gate self-alignment, then precise alignment is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines multiple lithographic masking steps into a single lithographic process that defines source, drain and gate regions simultaneously. This merging of masking operations maintains alignment precision through self-alignment while significantly reducing manufacturing complexity by eliminating sequential masking steps.
Solution Approach 2:
The single lithographic mask is segmented into multiple functional regions that define source, drain and gate areas. This segmentation allows precise definition of each electrode region in one exposure step, achieving alignment precision without requiring multiple masks and reducing manufacturing complexity.
4Reliability
If high-temperature processing is used for metal annealing, then ohmic contact quality is improved, but thermal budget increases and CMOS compatibility is reduced
Solution Approach 1:
The patent changes the annealing temperature parameter from high-temperature processing to low-temperature annealing (below 400°C). This parameter change maintains ohmic contact quality through optimized low-temperature annealing protocols while reducing the thermal budget to be compatible with subsequent CMOS processing steps.
Solution Approach 2:
The metal stack is prepared with preliminary layer结构设计 that enables effective ohmic contact formation at lower annealing temperatures. This preliminary structuring of the metal layers (such as Ti/Al/NiV stacks) allows the annealing process to achieve good contact quality without requiring high temperatures, thus protecting CMOS compatibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of scalable, CMOS-compatible GaN-based HEMTs with improved device performance, including high ON-OFF ratios and reduced thermal budget, facilitating the integration of GaN-based systems with Si CMOS platforms.
Implementation Method 1
employing a Ti/Al/NiV metal layering
Implementation Method 2
low-temperature annealing
Data Source
AI summary
A method for fabrication of high electron mobility transistor (HEMT) semiconductor devices is presented. The method includes providing a substrate, growing a HEMT layer structure on the substrate; and self-aligned common metal stack formation of source, drain and gate electrodes on the HEMT layer structure using a single lithographic mask.