Mismatch Cells Enhance Capacitance Difference for Accurate Data Detection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor memory devices, the half VDD bit line pre-charge scheme struggles with accurately detecting data as the operating voltage decreases, leading to increased threshold voltage of cell transistors, which complicates data detection and leakage current suppression, making the full VDD bit line pre-charge scheme more preferable to minimize threshold voltage influence on sense amplifiers.

Innovation Solution

The implementation of a semiconductor memory device with mismatch cells and a sense amplifying unit that pre-charges bit line pairs to the source voltage level, using mismatch cells with lower threshold voltages to enhance capacitance differences between bit lines and inverted bit lines during read operations, facilitating easier data detection by amplifying voltage differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a half VDD bit line pre-charge scheme is used, then the device complexity is reduced, but the measurement precision of data detection deteriorates as operating voltage decreases

Engineering Contradiction:
Improvebit line pre-charge scheme complexityVSAvoiddata detection accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent introduces mismatch cells that create intentional asymmetry in the bit line structure. Specifically, one bit line is connected to both a memory cell and a mismatch cell, while the other bit line is connected only to a memory cell. This asymmetric configuration creates a capacitance difference that generates a voltage difference during read operations, enabling accurate data detection even with full VDD pre-charge voltage.

Inventive Principle:
Principle #4Asymmetry

2Use of energy by moving object

If the operating voltage is lowered, then the power consumption is reduced, but the threshold voltage of cell transistors increases making data detection more difficult

Engineering Contradiction:
Improvepower consumptionVSAvoiddata detection difficulty
Core Design Contradiction:
Use of energy by moving objectVSDifficulty of detecting and measuring

Solution Approach 1:

The patent converts the harmful effect of increased threshold voltage (which makes data detection difficult) into a beneficial effect. By introducing mismatch cells with specifically designed threshold voltages, the patent creates a voltage difference between bit lines that compensates for the high threshold voltage effect. The mismatch cell's threshold voltage characteristics become the mechanism that enables detection rather than obstructing it.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Measurement precision

If mismatch cells are introduced to enhance capacitance differences, then the measurement precision of data detection is improved, but the device complexity increases

Engineering Contradiction:
Improvedata detection accuracyVSAvoidmemory cell array complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the memory cell array into distinct functional units: normal memory cells for data storage and mismatch cells for detection enhancement. The mismatch cells are strategically placed and connected only to one bit line, creating a modular structure that adds detection capability without completely redesigning the entire memory array. This segmentation allows the system to maintain its core functionality while adding the necessary asymmetry for accurate detection.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for more accurate data detection in semiconductor memory devices, particularly for data '1', by inducing capacitance mismatches and reducing the burden on boosting voltage generation, thereby improving read operations and reducing errors.

Implementation Method 1

The first and second mismatch cells may be selected together with a corresponding memory cell of the first and second memory cells to increase a capacitance difference between the bit lines and the inverted bit lines during a read operation.

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS8199592B2Semiconductor memory devices with mismatch cells
Publication Date: 2012.06.12 SAMSUNG ELECTRONICS CO LTD
  • US8199592B2 patent drawing
  • US8199592B2 patent drawing
  • US8199592B2 patent drawing

AI summary

A semiconductor memory device having the mismatch cell makes a capacitance difference between a bit line pair relatively large during a read operation using at least one dummy memory cell as a mismatch cell selected together with a corresponding memory cell. Therefore, data of a semiconductor memory device may be detected more easily.