Mismatch-Shaping DAC Logic for High-Linearity iADC Feedback
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Solution Overview
Problem
Incremental analog-to-digital converters (iADCs) face challenges in achieving DAC linearity due to quantization noise and mismatch shaping, which increases hardware complexity and latency, especially at high resolution and dynamic range.
Innovation Solution
A digital-to-analog converter (DAC) with a mismatch shaping logic block that uses a selection vector and switching blocks to split multi-bit words into sub-portions, adjusting weight factors to alleviate mismatch errors, thereby improving linearity and reducing hardware complexity and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If mismatch shaping circuit is added to improve DAC linearity, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The multi-bit word is segmented into multiple sub-words using switching blocks, where each sub-word controls a separate output element. This segmentation allows mismatch shaping to be implemented through simple switching operations rather than complex circuitry, resolving the contradiction between improving DAC linearity and reducing hardware complexity
Solution Approach 2:
Instead of directly shaping the mismatch through complex filtering circuits, the patent inverts the approach by using a mismatch shaping logic block that generates selection vectors to alternately activate different output elements. This indirect approach achieves mismatch shaping with simpler hardware, resolving the contradiction between manufacturing precision and device complexity
2Measurement precision
If complex decimation filters are used to achieve high resolution, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent extracts the essential mismatch shaping function from the complex decimation filter chain and implements it independently through the mismatch shaping logic block. This extraction allows high-resolution conversion to be achieved without the full complexity of traditional decimation filters, thereby reducing latency while maintaining measurement precision
Solution Approach 2:
The mismatch shaping is performed preliminarily through the logic block before the signal proceeds through the remaining conversion stages. By addressing the mismatch issue early in the conversion process through simple logic operations rather than requiring complex post-processing filters, the patent reduces overall conversion latency while maintaining high resolution
Data Source
AI summary
A DAC, for use in an iADC, is configured for converting a multi-bit word to an analog feedback signal. The DAC comprises a MMS logic block. It further comprises a plurality of output elements configured to generate respective analog portions based on a selection vector and a signal combiner for combining the analog portions to the analog feedback signal. In the MMS logic block switching blocks are arranged cascaded. Each switching block receives at least a portion of the multi-bit word, splits the portion into two sub-portions and forwards them to one subsequent switching block or to one output element. A weight factor is adjusted by multiplying it with the difference of the two sub-portions. A weight accumulator accumulates successive adjusted weight factors, wherein the way of splitting the portion of a further multi-bit word is determined based on the sign of the weight accumulator.