Mispredict Recovery Unit for Branch Pipeline Latency

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Solution Overview

Problem

Branch mispredictions in microprocessors lead to significant performance bottlenecks due to pipeline flushes and 'taken bubble penalties,' as existing branch predictors struggle with accuracy and latency, especially in deeper pipeline processors.

Innovation Solution

A mispredict recovery apparatus comprising a misprediction recovery unit (MRU) with a branch confidence filter, tag content-addressable memory (CAM), and mispredict recovery buffer (MRB) that generates prediction confidence information and stores alternate paths for frequently mispredicted branches, allowing for discrete cycle predictions and reducing latency by driving the instruction fetch pipeline with these alternate paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If complex branch predictor units are used to improve prediction accuracy, then branch prediction accuracy is improved, but prediction latency increases

Engineering Contradiction:
Improvebranch prediction accuracyVSAvoidprediction latency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The branch prediction system is segmented into multiple specialized predictors (e.g., local predictors, global predictors, pattern history tables) that operate in parallel or sequence. Each predictor handles specific types of branches or prediction patterns, allowing the system to achieve high accuracy without requiring a single complex predictor that would increase latency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary branch prediction using fast predictors before committing to final prediction decisions. Prediction outcomes are pre-computed and stored in prediction buffers, allowing the processor to prepare fetch queue adjustments in advance rather than reacting to mispredictions after they occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 3:

A prediction buffer acts as an intermediary between the branch predictors and the fetch queue. This buffer absorbs prediction latency by storing pre-computed prediction outcomes, decoupling the slow prediction process from the fast fetch operations and eliminating the direct latency penalty.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If the pipeline is flushed after a misprediction to correct the error, then prediction accuracy is restored, but performance deteriorates due to lost fetch cycles

Engineering Contradiction:
Improveprediction accuracyVSAvoidfetch throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The system maintains prediction buffers that cushion against misprediction penalties by storing multiple prediction outcomes in advance. When a misprediction occurs, the buffered predictions provide a cushion that allows the fetch queue to continue operating with minimal disruption, preventing complete pipeline flushes.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

Instead of flushing the entire pipeline on misprediction, the system selectively discards only the affected fetch queue entries while recovering and reusing valid predictions from buffers. This partial recovery approach maintains throughput by preserving instructions that are not affected by the misprediction.

Inventive Principle:
Principle #34Discarding and recovering

Solution Approach 3:

The system implements feedback mechanisms where misprediction outcomes are used to update predictor states and adjust future predictions. This feedback loop allows the system to learn from errors and improve accuracy without requiring aggressive pipeline flushing, as corrections can be made incrementally through predictor state updates.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10846097B2Mispredict recovery apparatus and method for branch and fetch pipelines
Publication Date: 2020.11.24 SAMSUNG ELECTRONICS CO LTD
  • US10846097B2 patent drawing
  • US10846097B2 patent drawing
  • US10846097B2 patent drawing

AI summary

The present disclosure includes a mispredict recovery apparatus, which may comprise an instruction execution unit, a branch predictor, and a misprediction recovery unit (MRU). The MRU may provide discrete cycle predictions after a misprediction redirect from the instruction execution unit. The MRU may include a branch confidence filter to generate prediction confidence information for predicted branches. The MRU may include a tag content-addressable memory (CAM). The tag CAM may store frequently mispredicting low-confidence branches, probe the misprediction redirect, and obtain the prediction confidence information from the branch confidence filter. The MRU may include a mispredict recovery buffer (MRB) to store an alternate path for frequently mispredicting low-confidence branches present in the tag CAM without storing the instructions themselves. Also disclosed is a method for recovering from mispredicts associated with the instruction fetch pipeline.