MISD Processor Architecture for Secure Avionics
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Solution Overview
Problem
Conventional computer systems face challenges in ensuring high security, reliability, and integrity, particularly when executing multiple threads, as they often lead to inefficient resource utilization, increased power consumption, and size, making them unsuitable for embedded applications.
Innovation Solution
A multiple instruction stream, single data stream (MISD) processor architecture with a master instruction processing unit, multiple fetch instruction processing units, a single bus interface/memory unit, and a single data processing unit, along with a supervisor fetch unit and user process fetch units, which allows for secure, reliable, and efficient execution of multiple independent processes with predictable behavior and resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple threads are executed simultaneously on a single microprocessor, then computing efficiency is improved, but security and reliability are worsened due to increased unpredictability and resource contention
Solution Approach 1:
The processor is segmented into multiple independent execution units (EU0, EU1, EU2, etc.), each capable of executing a separate thread independently. Each execution unit has its own instruction fetch unit, decode unit, and execution resources, allowing simultaneous execution of multiple threads while maintaining isolation and predictability for each thread's resource consumption.
Solution Approach 2:
A supervisor unit acts as an intermediary between multiple execution units and shared resources (memory, I/O). The supervisor allocates time slots to different execution units, mediates resource access, and ensures that each thread receives guaranteed processing time and resources, preventing resource contention and maintaining security boundaries.
2Reliability
If a restricted single processor is used to execute a single program, then security and reliability are improved, but processing capability is wasted and more processors are required
Solution Approach 1:
Multiple execution units are merged into a single processor package with shared control logic and resources. The processor combines the security and reliability of restricted execution with the productivity of parallel processing by allowing multiple threads to execute simultaneously on different execution units while maintaining isolation through the supervisor's time-slot allocation.
Solution Approach 2:
Each execution unit is designed to be universal and can execute any thread or program independently. The processor can dynamically allocate different threads to different execution units based on security requirements and resource needs, making the system multi-functional while maintaining the security properties of restricted execution.
3Productivity
If multiple processing techniques are used to execute multiple applications simultaneously, then computing efficiency is improved, but it becomes difficult to guarantee data security, reliability and integrity
Solution Approach 1:
The processor implements dynamic time-slot allocation where the supervisor can adjust the time slots assigned to each execution unit based on real-time requirements. This dynamic allocation allows the system to adapt to changing security and performance needs while maintaining guaranteed resource allocation, making it easier to guarantee security compared to static multi-processing approaches.
Solution Approach 2:
The supervisor receives feedback from execution units about their execution status, resource consumption, and any security violations. Based on this feedback, the supervisor can adjust time slot allocations, prevent resource contention, and respond to security events, making security guarantee more manageable through continuous monitoring and adaptation.
Data Source
AI summary
A computing system can be optimized for high security, reliability and/or integrity. The computing system can include a multiple instruction stream, single data stream processor. The multiple instruction stream, single data stream processor can include a master instruction processing unit, fetch instruction processing units, a single bus interface/memory unit, and a single data processing unit. The computing system can also include a storage device or a memory. The processor can be utilized in numerous applications including avionics software applications.