MISR Compaction Using Control Signals for Deterministic ATPG Responses
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Solution Overview
Problem
Existing integrated circuit (IC) test methods face challenges in accurately compacting scan chain output responses due to unknown/indeterministic values, which can corrupt on-chip multiple-input shift register (MISR) signatures and reduce the accuracy of scan tests.
Innovation Solution
A system that includes a processing engine to generate a control signal for an on-chip MISR, allowing only deterministic output responses to be compacted and compared with expected signatures, thereby blocking unknown/indeterministic values and improving test accuracy. This system also includes a scan test controller with a multiple-input signature register (MISR) configured to receive deterministic output responses, generate signatures, and provide a test status signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If scan chain output responses are compacted into on-chip MISR, then test memory usage is reduced, but unknown/indeterministic values corrupt MISR signatures and reduce test accuracy
Solution Approach 1:
The patent applies preliminary action by pre-calculating expected scan chain output responses during design time and comparing them with actual responses during testing. The expected responses are stored in test memory and used as reference to validate actual responses, preventing corruption by unknown values. This pre-computation approach allows the system to identify and handle indeterministic values before they can corrupt the MISR signatures.
Solution Approach 2:
The patent introduces an intermediary mechanism by using expected response values as a mediator between the actual scan chain outputs and the MISR compaction process. The expected responses act as a reference layer that validates whether actual responses are deterministic before allowing them to be compacted into MISR, thus protecting against corruption while maintaining memory efficiency.
2Measurement precision
If scan chain output responses are shifted out to top-level pads for comparison, then test accuracy is maintained, but design complexity and test time increase
Solution Approach 1:
The patent extracts only the necessary information (deterministic response values) from the scan chain outputs for compaction into MISR, while leaving the full response validation to be performed through comparison with pre-stored expected values. This extraction approach maintains test accuracy without requiring all responses to be shifted out to pads, thereby reducing design complexity.
Solution Approach 2:
The patent uses copying by storing expected scan chain output responses in test memory during design time. These copied expected values are then used during testing to compare against actual responses, eliminating the need to shift all actual responses out to pads for comparison. This copying mechanism maintains test accuracy while simplifying the hardware design.
3Productivity
If multiple designs are tested simultaneously using pipeline circuits, then productivity increases, but test memory footprint increases
Solution Approach 1:
The patent applies segmentation by dividing the testing process into separate pipeline stages, where each design under test has its own scan chains and expected response storage. This segmentation allows multiple designs to be tested simultaneously in different pipeline stages without requiring all test data to be stored in a single large memory block, thereby managing memory footprint while maintaining high productivity.
Solution Approach 2:
The patent transitions to another dimension by using time-multiplexed pipeline testing instead of spatial parallelism. Multiple designs are tested in sequence through pipeline stages rather than simultaneously in separate physical test paths, reducing the memory footprint required for storing expected responses while maintaining high testing throughput through efficient time utilization.
Data Source
AI summary
Apparatus and associated methods relate to compacting scan chain output responses of vectors into an on-chip multiple-input shift register (MISR) in the presence of unknown/indeterministic values X in design. In an illustrative example, a system may include a processing engine configured to generate a control signal for a MISR, and the control signal may hold information of what cycle has deterministic output response. The MISR may be configured to compact deterministic output responses of actual scan chain output responses in response to the decoded control signal and compare on-chip MISR signatures with expected MISR signatures to generate pass/fail status of the test. By using the system, unknown/indeterministic values X on the output responses may be blocked from being compacted into the MISR. Accordingly, the on-chip MISR signatures may not be corrupted by the unknown/indeterministic values X, and accuracy of the scan test may be advantageously improved.