MISR Shadow Logic for On-Chip Defect Identification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As die sizes increase, the ratio of test pins to die size decreases, making it unfeasible to allocate separate test pins for each functional region, and existing post-processing software in automatic test equipment (ATE) requires excessive time and resources to identify defective regions due to data intermixing between functional regions.
Innovation Solution
A computer-implemented method using multiple input signature registers (MISRs) and their shadows to generate a consolidated status indicator, optimizing resource usage by combining responses to multiple test patterns and reducing the number of bits in shadow data, enabling efficient identification of defective functional regions with minimal ATE resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate test pins are allocated for testing each functional region, then testing coverage and defect identification accuracy are improved, but device complexity and resource requirements increase beyond feasible limits
Solution Approach 1:
The patent combines multiple test responses from different functional regions into a single consolidated test response. Instead of using separate test pins for each functional region, the system merges the test responses and uses a single pin to output the combined result, thereby reducing the number of pins required while maintaining comprehensive testing coverage
Solution Approach 2:
The test response merging logic serves multiple functional regions simultaneously through a single output pin. This multi-functional approach allows one pin to perform what would traditionally require multiple dedicated pins, reducing overall device complexity while preserving the ability to identify defects across all tested regions
2Measurement precision
If post processing software is implemented in automatic test equipment to handle intermixed data, then comprehensive testing of multiple functional regions is achieved, but test time and ATE resources such as memory are excessively consumed
Solution Approach 1:
The patent performs test response merging during the testing process itself, rather than as a subsequent post-processing step. By consolidating multiple test responses into a single response in real-time during testing, the system eliminates the need for time-consuming post-processing software operations and reduces overall test time
Solution Approach 2:
The testing system performs the merging operation internally through dedicated logic circuits that are part of the test architecture. This self-service approach allows the system to handle its own data consolidation needs without requiring external post-processing software, thereby reducing ATE resource consumption and test time
3Measurement precision
If post processing software is implemented in automatic test equipment to handle intermixed data, then comprehensive testing of multiple functional regions is achieved, but ATE resources such as memory are excessively consumed
Solution Approach 1:
The patent combines multiple test responses into a single consolidated response using dedicated merging logic, thereby reducing the volume of data that needs to be stored and processed. This approach minimizes memory requirements by eliminating the need to retain separate response data for multiple functional regions
Solution Approach 2:
The system uses simple, resource-efficient merging logic that requires minimal memory resources compared to complex post-processing software. The merging operation is performed using basic logical operations that consume minimal ATE resources, making the testing process scalable and resource-friendly
Data Source
AI summary
In one embodiment, a multiple input signature register (MISR) shadow works with a MISR to compress test responses of a layout partition in a functional region of an integrated circuit. In operation, for each test pattern in a test pattern split, the MISR generates a MISR signature based on the responses of the layout partition. As the test patterns in the test pattern split execute, the MISR shadow accumulates the MISR signatures and stores the result as MISR shadow data. After the final test pattern included in the test pattern split executes, the MISR shadow combines the bits in the MISR shadow data to form a single bit MISR shadow status that indicates whether the layout partition, and therefore the functional region, responds properly to the test pattern split. By efficiently summarizing the test responses, the MISR shadow optimizes the resources required to identify defective functional regions.