Missing Clock Switching Circuit for Glitch-Free Failover
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Solution Overview
Problem
Clock switching circuits in ASICs face issues with glitches during power up and fail to switch to alternate clock sources when the selected source is faulty or missing, leading to deadlocks due to unsynchronized enable signals and feedback loops.
Innovation Solution
The proposed solution includes a clock switching circuit with enable synchronization logic, a priority multiplexer, and a missing clock detection circuit that breaks feedback paths to prevent glitches and enable seamless switching between clock sources by using asynchronous resets and feedback signals to manage clock enables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous reset is used to CLK2 domain flip flops to solve power up glitches, then power up reliability is improved, but recovery or removal violation occurs on the flip flop which drives the enable of CLK2
Solution Approach 1:
An intermediary circuit (the enable synchronization logic with priority multiplexer) is introduced between the reset signal and the CLK2 enable flip flop. This intermediary ensures that the flip flop is properly synchronized before reset is released, preventing recovery/removal violations while maintaining power up reliability.
Solution Approach 2:
The circuit performs preliminary synchronization of the enable signal before the reset is released. By ensuring the flip flop is in a known state before asynchronous reset is released, the circuit prevents timing violations during power up while maintaining reliability.
2Adaptability or versatility
If clock switching circuit switches between asynchronous clock sources, then adaptability is improved, but glitches are generated at the output during and after power up
Solution Approach 1:
The circuit uses feedback from the enable synchronization logic to control the priority multiplexer. The feedback mechanism ensures that the output clock is only switched when the enable signal is properly synchronized, preventing glitches while maintaining adaptability for clock source selection.
Solution Approach 2:
The enable synchronization logic dynamically adjusts the enable signal based on the clock domain synchronization status. This dynamic control ensures smooth transitions between clock sources without generating glitches at the output.
3Reliability
If feedback path is maintained for clock monitoring, then fault detection capability is improved, but deadlock occurs when selected clock source is missing or faulty
Solution Approach 1:
The priority multiplexer acts as an intermediary that breaks the feedback path when the enable signal is not properly synchronized. This prevents deadlock conditions while maintaining the ability to detect faulty clock sources through the monitoring circuitry.
Solution Approach 2:
The circuit takes preliminary action to prevent deadlock by breaking the feedback path before it can cause a deadlock condition. When the enable signal is not properly synchronized, the feedback path is broken to prevent the deadlock that would otherwise occur.
Data Source
AI summary
A glitch free clock switching circuit includes a first enable synchronization logic that generates a first clock enable in response to a first enable from a first enable generation logic. The clock switching circuit includes a second enable synchronization logic that generates a second clock enable in response to a second enable from a second enable generation logic. A logic gate is coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high. A priority multiplexer receives a first clock signal, the first enable and the logic gate output. The multiplexer configured to select the first clock signal as the clock output if the first enable is logic high, irrespective of the logic gate output.