Missing Interrupt Detector Circuit for Reliable Signal Propagation
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Solution Overview
Problem
In microprocessor-based systems, missing interrupts occur due to rapid succession of interrupts or spurious events, leading to loss of communication between devices and the CPU, with existing solutions like debounce delay logic being system-specific and unable to handle both edge and level triggered interrupts effectively.
Innovation Solution
A hardware-based approach that detects and resends missing interrupts using a missing interrupt timer, independent of debounce delay logic, allowing for detection and resending in systems with both edge and level triggered interrupts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If debounce delay logic is used to handle missing interrupts, then system-specific interrupt handling is improved, but the solution cannot handle both edge and level triggered interrupts effectively
Solution Approach 1:
A missing interrupt detector circuit is introduced as an intermediary component between the interrupt source and the processor. This detector monitors interrupt signals and automatically detects missing interrupts, then resends them through the interrupt line. The detector acts as a mediator that handles both edge and level triggered interrupts universally, eliminating the need for system-specific debounce delay logic while maintaining reliable interrupt service.
2Measurement precision
If a timer-based detection mechanism is implemented, then missing interrupt detection accuracy is improved, but additional hardware components are required
Solution Approach 1:
The missing interrupt detector circuit performs self-service by automatically monitoring its own interrupt line, detecting missing interrupts, and resending them without external intervention. The circuit uses a timer that is already present in the system (or a simple counter) to determine if an interrupt was missed, eliminating the need for complex external monitoring hardware while maintaining high detection accuracy.
3Speed
If rapid succession of interrupts is allowed, then interrupt response speed is improved, but missing interrupts occur due to processor overload
Solution Approach 1:
The missing interrupt detector performs preliminary action by proactively monitoring interrupt signals and detecting missing interrupts before they are lost. When the processor is overloaded and cannot service interrupts in rapid succession, the detector catches these missed interrupts and resends them, ensuring reliable interrupt delivery without limiting the speed at which interrupts can be generated or responded to.
Data Source
AI summary
A circuit may receive an interrupt associated with a device. The interrupt may be sent by the device via an interrupt line associated with the device. The circuit may send the interrupt associated with the device. The interrupt may be sent via an interrupt line associated with the circuit. The circuit may start a missing interrupt timer, associated with the interrupt, based on sending the interrupt. The missing interrupt timer may be associated with a threshold amount of time by which the interrupt is to be serviced. The circuit may identify, based on the missing interrupt timer, the interrupt as a missing interrupt. The circuit may resend the missing interrupt via the interrupt line associated with the circuit. The missing interrupt may be resent to cause the missing interrupt to be serviced.