Mixed 6T and 12T Configuration Memory for SEU-Hardened Programmable ICs
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Solution Overview
Problem
Traditional programmable integrated circuits (ICs) face increased likelihood of single event upsets (SEUs) due to smaller chip geometries and lower supply voltages, leading to reduced mean time to failure and higher failure rates, as cosmic and alpha particles can alter the state of configuration memory cells.
Innovation Solution
Implementing a programmable IC with a mix of 6T and 12T SRAM configuration memory cells, where critical portions of the circuit design are programmed using 12T cells for redundancy and non-critical portions using 6T cells, with a voting circuit also implemented using 12T cells to mitigate SEUs, while maintaining a comparable footprint to all 6T SRAM ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 12T SRAM configuration memory cells are used for critical portions of the circuit design, then the single event upset failure rate is reduced, but the IC footprint increases
Solution Approach 1:
The patent applies local quality by using different types of SRAM configuration memory cells (6T or 12T) in different regions of the IC based on the criticality of the circuit design portions. Critical portions are implemented with 12T cells for higher reliability, while non-critical portions use 6T cells to minimize footprint, thus resolving the contradiction between reliability and area.
2Adaptability or versatility
If a mix of 6T and 12T SRAM cells is used, then flexibility in reducing failure rate is enhanced, but device complexity increases
Solution Approach 1:
The patent changes the parameter of configuration memory cell type (6T vs 12T) to adjust the failure rate characteristics. By selecting different cell types based on circuit criticality, the system gains flexibility in achieving desired reliability levels while managing the complexity through systematic parameter selection rather than uniform design.
Data Source
AI summary
To implement a circuit design on a programmable integrated circuit (IC), first data are generated for implementing the circuit design. Critical and non-critical portions of the circuit design are determined, and second data are generated for programming configuration memory cells of the programmable IC to implement the circuit design. A first subset of the second data is assigned to program a first type of configuration memory cells to implement the critical portion of the circuit design on a first subset of programmable logic resources and a first subset of programmable interconnect resources of the programmable IC. A second subset of the second data is assigned to program a second type of configuration memory cells to implement the non-critical portion of the circuit design on a second subset of programmable logic resources and a second subset of programmable interconnect resources. The second data are stored in an electronically readable storage medium.