Mixed-Transistor Adder Tree Layout for Low-Power Arithmetic
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Solution Overview
Problem
Existing adder trees in binary arithmetic circuits face challenges in achieving low power consumption and silicon area efficiency while maintaining speed and driving strength.
Innovation Solution
The implementation of an adder tree structure that interleaves full adders with varying transistor counts, specifically using 28-transistor and 14-transistor adders, arranged in specific patterns to optimize silicon area and power consumption without significant speed impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional 28-transistor full adders are used throughout the adder tree, then driving strength and speed are maintained, but silicon area and power consumption increase
Solution Approach 1:
The patent applies local quality by using different transistor counts for full adders based on their position in the adder tree. Internal full adders (not on the critical path) use 14 transistors to reduce area and power, while full adders on the critical path use 28 transistors to maintain driving strength and speed. This selective approach optimizes the overall circuit by applying different quality levels to different locations.
Solution Approach 2:
The adder tree is segmented into different types of full adders: 14T FAs for internal nodes and 28T FAs for critical path nodes. This segmentation allows the circuit to be divided into functional zones with different performance requirements, enabling area optimization in non-critical regions while maintaining speed in critical regions.
2Reliability
If traditional 28-transistor full adders are used throughout the adder tree, then driving strength is maintained, but power consumption increases
Solution Approach 1:
The patent reduces power consumption by applying local quality optimization: 14T full adders are used in non-critical positions where full driving strength is not required, thereby reducing dynamic power consumption. Meanwhile, 28T full adders are strategically placed on the critical path to maintain necessary driving strength and signal integrity where speed is paramount.
3Area of stationary object
If 14-transistor full adders are used to reduce silicon area, then area efficiency improves, but speed and driving strength deteriorate
Solution Approach 1:
The adder tree is segmented into critical path positions and non-critical positions. 14T full adders are deployed in non-critical positions to achieve area efficiency, while 28T full adders are placed on the critical path to ensure high-speed operation and adequate driving strength. This segmentation resolves the contradiction by applying area optimization only where it does not impact overall performance.
4Area of stationary object
If mixed 14T and 28T full adders are interleaved, then silicon area and power consumption are reduced, but circuit complexity increases
Solution Approach 1:
The patent introduces asymmetry in the adder tree structure by interleaving 14T and 28T full adders in a systematic pattern rather than using uniform adders throughout. This asymmetric arrangement, guided by critical path analysis, achieves area and power optimization while maintaining manageable design complexity through structured placement rules.
Data Source
AI summary
In some aspects of the present disclosure, an adder tree circuit is disclosed. In some aspects, the adder tree circuit includes a plurality of full adders (FAs) including: a first subgroup of FAs, wherein each FA of the first subgroup includes a first number of transistors; and a second subgroup of FAs, wherein each FA of the second subgroup includes a second number of transistors, the first number being greater than the second number; wherein each FA of the first subgroup receives a first input from a first one of the second subgroup of FAs and a second input from a second one of the second subgroup of FAs, and each FA provides a first output to a third one of the second subgroup of FAs and a second output to a fourth one of the second subgroup of FAs.