Semiconductor Layout Support for Mixed Breakdown Voltage Regions

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Solution Overview

Problem

Conventional layout design support apparatuses struggle to accurately identify equipotential regions when circuit elements with different breakdown voltages coexist on a semiconductor chip, leading to inefficient layout design and potential chip size increase.

Innovation Solution

A layout design support apparatus that determines whether to short-circuit terminals in circuit elements based on element type and breakdown voltage information, identifying equipotential regions by adding potential labels to circuit components, allowing for precise layout optimization even when elements with varying breakdown voltages are present.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the entire chip is designed with a breakdown voltage corresponding to the high voltage VH, then the circuit element H can obtain sufficient breakdown voltage, but the layout area of the entire chip becomes large

Engineering Contradiction:
Improvebreakdown voltageVSAvoidlayout area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by designing different breakdown voltage characteristics for different regions of the chip. High voltage circuit elements are placed in regions with higher breakdown voltage characteristics, while low voltage circuit elements are placed in regions with lower breakdown voltage characteristics. This allows each region to be optimized for its specific voltage requirements, preventing the entire chip from requiring high breakdown voltage design, thereby reducing overall layout area.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If the entire chip is designed with a breakdown voltage corresponding to the low voltage VL, then the layout area of the entire chip becomes small, but the circuit element H cannot obtain a sufficient breakdown voltage

Engineering Contradiction:
Improvelayout areaVSAvoidbreakdown voltage
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent segments the chip into different regions based on voltage requirements. By dividing the chip into high voltage and low voltage regions, each region can be designed with appropriate breakdown voltage characteristics. This segmentation allows the low voltage region to have smaller dimensions and closer spacing, reducing overall chip area, while the high voltage region maintains sufficient breakdown voltage for its circuit elements.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If circuit elements with different breakdown voltages coexist on one chip, then the functionality of the integrated circuit is enhanced, but the layout design becomes complex

Engineering Contradiction:
ImprovefunctionalityVSAvoidlayout design complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent manages layout design complexity by implementing local quality through region-specific breakdown voltage characteristics. By clearly defining high voltage and low voltage regions with distinct electrical characteristics, the patent simplifies the layout design process. Designers can focus on optimizing each region independently according to its voltage requirements, rather than dealing with uniform complex design rules across the entire chip.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12412021B2Layout design support apparatus, layout design support method, and manufacturing method of semiconductor device
Publication Date: 2025.09.09 ABLIC INC
  • US12412021B2 patent drawing
  • US12412021B2 patent drawing
  • US12412021B2 patent drawing

AI summary

A layout design support apparatus 100 determines, in a circuit element connected to a first external terminal P1 to which a first potential identification label is added, whether to short-circuit one terminal connected to the first external terminal P1 and another terminal based on a determination criterion according to element type information and breakdown voltage information, adds the first potential identification label to the circuit components on a path from the first external terminal P1 to the one terminal of the circuit element to identify a first equipotential region according to determining not to short-circuit, repeatedly performs determination for the circuit element connected to the another terminal and identifies the first equipotential region according to determining to short-circuit, and identifies a second equipotential region when receiving a second potential identification label to be added to a second external terminal P2.