Mixed Cell Memory Controller for Power and Density Trade-offs
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Solution Overview
Problem
Current memory systems in multi-processor systems face challenges in reducing power consumption and memory real estate while increasing memory capacity and density, as adding more components increases power requirements and space, leading to costly cooling needs and inefficient memory allocation.
Innovation Solution
A memory controller that allocates memory content sensitively by distinguishing between performance-sensitive content and less demanding content, using a mixed cell memory system that combines Single Level per Cell (SLC) and Multiple Level per Cell (MLC) storage, allowing for dynamic allocation of DRAM and Storage Class Memory (SCM) based on application and thread requirements, thereby optimizing memory usage and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity and density are increased by adding more components, then memory capacity is improved, but power consumption and space requirements increase
Solution Approach 1:
The patent applies local quality by creating a mixed cell memory system where different regions have different cell densities. Specifically, it uses both Single Level Cell (SLC) and Multiple Level Cell (MLC) memory regions within the same memory system. The SLC region provides higher performance with lower density, while the MLC region provides higher density with acceptable performance. This allows the system to allocate memory based on local quality requirements - performance-critical applications use SLC while less demanding applications use MLC, thereby increasing overall memory capacity without proportionally increasing power consumption.
2Quantity of substance
If memory capacity and density are increased by adding more components, then memory capacity is improved, but space requirements and cooling needs increase
Solution Approach 1:
The patent merges SLC and MLC memory technologies into a single mixed cell memory system. By combining these two different memory cell types in one integrated memory system with unified control logic, the patent achieves higher overall memory capacity within the same physical footprint. The memory controller dynamically manages both SLC and MLC regions, allowing the system to pack more total memory capacity into the same chip area compared to using only one memory type, thereby reducing memory real estate requirements.
3Ease of operation
If all memory is allocated uniformly to all processors, then simplicity of allocation is maintained, but memory allocation efficiency decreases
Solution Approach 1:
The patent implements dynamic memory allocation where the memory controller can dynamically assign SLC or MLC memory regions to different processors or memory requests based on real-time performance requirements. The system monitors application performance needs and dynamically allocates high-performance SLC memory to latency-sensitive applications while assigning MLC memory to bandwidth-intensive or less time-critical applications. This dynamic approach maintains ease of operation through automated controller management while dramatically improving memory allocation efficiency compared to static uniform allocation.
4Speed
If higher performance memory is used throughout the system, then system performance is improved, but power consumption and cost increase
Solution Approach 1:
The patent changes the memory cell density parameter to create a spectrum of performance levels. By using SLC memory with lower cell density for performance-critical regions and MLC memory with higher cell density for less critical regions, the system optimizes the performance-power tradeoff. The memory controller can change operational parameters such as access timing and voltage levels based on whether SLC or MLC memory is being accessed, thereby achieving high system performance where needed while reducing overall power consumption through the use of more energy-efficient MLC memory in appropriate regions.
Data Source
AI summary
A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).