Mixed CFET and Unipolar Semiconductor Structure Without Extra Lithography
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Solution Overview
Problem
Complementary field-effect transistors (CFETs) are less attractive for peripheral logic cells requiring unipolar devices due to the need for additional photolithography processes to match conductivity types, hindering high integration density in semiconductor manufacturing.
Innovation Solution
A semiconductor structure is developed with a CFET region for stacked devices and a unipolar region for non-stacked devices, using a laminated structure with alternating layers of channel and sacrificial materials to streamline manufacturing, allowing for the formation of both CFET and unipolar devices on the same substrate with different configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CFET stacking is used to achieve higher transistor density, then device density is improved, but additional photolithography processes are required to match conductivity types
Solution Approach 1:
The substrate is divided into a CFET region and a unipolar region, allowing different device configurations to coexist on the same wafer. The CFET region implements stacked transistors for high density, while the unipolar region implements planar transistors for simplified manufacturing, thus resolving the contradiction between density and process complexity
Solution Approach 2:
Different regions of the substrate are assigned different device structures tailored to their specific functional requirements. The CFET region uses stacked configuration where conductivity type matching is critical, while the unipolar region uses planar configuration where such matching is less critical, allowing each region to optimize for its specific needs
2Reliability
If additional photolithography processes are added to match conductivity types, then CFET performance is improved, but manufacturing complexity increases
Solution Approach 1:
By segmenting the wafer into CFET and unipolar regions, the patent allows CFET devices to receive the full benefit of conductivity-matched stacked structures where reliability is paramount, while unipolar devices use simpler planar structures where such complexity is unnecessary, thus maintaining reliability where needed while improving ease of manufacture overall
Solution Approach 2:
The unipolar region acts as a sacrificial or alternative path that absorbs the manufacturing simplicity requirement, allowing the CFET region to focus on performance and reliability without being constrained by the need to simplify processes across the entire wafer
Data Source
AI summary
A semiconductor structure includes a substrate, a first device unit and a second device unit. The substrate includes a first region and a second region. The first device unit is disposed on the first region, and includes a plurality of first channel portions and two first source/drain portions. The second device unit is disposed on the second region, and includes a lower device and an upper device. The lower device is disposed on the second region, and includes at least one lower channel portion and two lower source/drain portions. The upper device is disposed above and spaced apart from the lower device, and includes at least one upper channel portion and two upper source/drain portions. A number of the first channel portions is greater than a number of the at least one lower channel portion and greater than a number of the at least one upper channel portion.