Mixed Clock Domain Signaling in LED Packages for Cascade Integrity
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Solution Overview
Problem
Conventional LED display systems face challenges with high pixel pitch and increased complexity due to the need for multiple uncorrelated clock domains, leading to sampling jitter and data integrity loss, especially in high-resolution displays.
Innovation Solution
Implement mixed clock domain signaling where the bit period is maintained and correlated to the original clock domain throughout cascade communication, using a local clock domain for each LED package to reduce sampling jitter and maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple uncorrelated clock domains are used in LED cascade communication, then local timing control is improved, but sampling jitter increases and data integrity is lost
Solution Approach 1:
The patent segments the clock domain into two distinct parts: an original clock domain that maintains the bit period timing for data validity, and a local clock domain that provides timing for internal logic operations. This segmentation allows each clock domain to serve its specific function independently, preventing the sampling jitter that occurs when a single clock domain must serve multiple conflicting timing requirements.
Solution Approach 2:
The patent introduces an intermediary mechanism (the mixed clock domain signaling protocol) that bridges the original clock domain and local clock domain. The bit period from the original clock domain acts as a timing reference that mediates between the master controller's clock and each LED package's local clock, ensuring that data sampling occurs at the correct moments despite local clock variations.
2Reliability
If additional clock recovery hardware is added to maintain data integrity, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent enables the LED packages to self-synchronize using the mixed clock domain signaling protocol without requiring external clock recovery hardware. Each LED package uses its local clock domain in conjunction with the original clock domain timing information to automatically align its sampling operations, making the system self-synchronizing and eliminating the need for additional hardware.
3Measurement precision
If pixel pitch is decreased for higher resolution displays, then display resolution is improved, but the number of electrical devices increases leading to higher complexity
Solution Approach 1:
The patent extracts the clock recovery function from the LED packages and places it in the domain of the original clock domain signaling. By removing the need for separate clock recovery hardware at each LED package, the patent reduces the electrical device density required in high-resolution displays while maintaining data integrity across cascaded LED packages with small pixel pitches.
Data Source
AI summary
Mixed clock domain signaling and, more particularly, mixed clock domain signaling for light-emitting diode (LED) packages arranged for cascade communication is disclosed. Mixed clock domain signaling involves digital communication where time-positions of bit pulse edges in a communication channel are derived from multiple uncorrelated clock domains, including an original clock domain from a master controller and a local clock domain. In the context of LED displays, serial strings of LED packages are arranged as LED pixels to receive cascade communication signals, and the original clock domain is derived from a master controller and a local clock domain is derived at each LED package. By providing for the bit period to be maintained and correlated to the original clock domain throughout the repeated cascade communication, problems associated with multiple uncorrelated clock domains in the communication channel, such as sampling jitter, may be averted, thus avoiding loss of data integrity.