Mixed CMOS Cell Layout to Reduce Threshold-Voltage Variation
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Solution Overview
Problem
Current semiconductor devices with uniform CMOS architectures are susceptible to layout-dependent effects such as increased rounding of structures and threshold-voltage variation due to substantial step-changes in intersection-location, which affect transistor performance.
Innovation Solution
A mixed CMOS architecture is introduced, featuring stacked half-height CFET cell regions with abutting single height non-CFET cell regions, minimizing substantial step-changes in intersection-location and reducing layout-dependent effects by using a stratified arrangement of active layers with heterogeneous dopant types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If uniform CMOS architecture with stacked cell regions of different heights is used, then transistor density is increased, but layout-dependent effects such as rounding of structures and threshold-voltage variation increase
Solution Approach 1:
The semiconductor device is divided into multiple cell regions with different heights (first cell regions of first height, second cell regions of second height). This segmentation allows the device to maintain high transistor density through vertical stacking while reducing layout-dependent effects by creating distinct zones with controlled interfaces, thereby resolving the contradiction between increased density and reduced manufacturing precision issues
Solution Approach 2:
Different cell regions are assigned different heights and configurations optimized for their specific functions. The first cell regions have first height optimized for certain transistors, while second cell regions have second height optimized for other transistors. This local optimization allows each region to achieve optimal performance while the overall device maintains high density without excessive layout-dependent effects
Data Source
AI summary
A semiconductor device (having a CMOS architecture) includes first to fourth cell regions Each of the first and second cell regions includes a pair of first and second stacks of nanosheets relative to, e.g., the Z-axis. The nanosheets of the first stack have a first dopant-type, e.g., N-type. The nanosheets of the second stack have a second dopant type, e.g., P-type. Each pair of first and second stacks represents a CMOS architecture relative to a second direction, e.g., the Y-axis Each of the third and fourth cell regions has CFET architecture, the CFET architecture being a type of CMOS architecture relative to the Z-axis. The third and fourth cell regions are adjacent each other relative to the Y-axis. The first and second active regions are on corresponding first and second sides of each of the third and fourth active regions. The first and second cell regions are non-CFET cell regions.