Semiconductor Package With Mixed Copper Pillar Sizes
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Solution Overview
Problem
Conventional flip-chip semiconductor packages using single copper pillar sizes face challenges in meeting electrical constraints for high-speed or power-consuming applications, as smaller pillars are insufficient and larger pillars require increased die size.
Innovation Solution
A semiconductor package design incorporating mixed copper pillar sizes, with smaller and larger vias and bump pads on the die, allowing for both die-to-die and die-to-substrate connections, and an underfill layer to manage thermal stress, enabling efficient signal and power transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a smaller copper pillar size is used to meet huge amount of die-to-die connections, then the pitch is reduced and connection density is increased, but the electrical constraints for high-speed or power-consuming IP cannot be met
Solution Approach 1:
The patent applies different copper pillar sizes to different functional regions of the semiconductor die. First copper pillars with first size are formed on first bump pads for die-to-die connections, while second copper pillars with second size (larger than first size) are formed on second bump pads for high-speed or power-consuming connections. This local differentiation allows each region to have optimal pillar size for its specific electrical requirements.
2Reliability
If a larger size of the copper pillar is used to meet electrical constraints, then the electrical performance is improved, but the die size greatly increases
Solution Approach 1:
The patent implements a mixed copper pillar structure where only specific bump pads requiring high electrical performance use larger second copper pillars, while other bump pads use smaller first copper pillars. This localized approach ensures electrical constraints are met only where necessary, avoiding the need to increase die size across the entire device.
Solution Approach 2:
The semiconductor die is segmented into different functional regions with different bump pad sizes and corresponding copper pillar sizes. The die includes first bump pads with first copper pillars for standard connections and second bump pads with second copper pillars for high-speed/power connections. This segmentation allows optimization of electrical performance in specific areas without increasing overall die size.
Data Source
AI summary
A semiconductor package includes a substrate and a flip-chip on the substrate The flip-chip includes first bump pads and second bump pads on an active surface of the flip-chip. Vias are disposed on the second bump pads. The first bump pads have a pad size that is smaller than that of the second bump pads. An underfill layer is disposed between the flip-chip and the substrate to surround the vias. The underfill layer is in direct contact with a surface of each of the first bump pads.