Mixed-Device Multilevel Inverter Deadtime for Overvoltage Stress
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Solution Overview
Problem
Multi-level voltage source power inverters face challenges due to excessive bus voltage stress on switching devices, leading to reduced lifetime or failure, particularly when latencies occur during state changes or faults, especially when using mixed high-frequency and low-frequency switching devices.
Innovation Solution
Implementing a mixed device type topology with high-frequency SiC MOSFETs for PWM switching and low-frequency IGBTs for directional switching, and adjusting deadtime requirements to prevent overvoltage stress, including extending the high-frequency switching devices' deadtime to match the low-frequency devices' commutation time, and using full bus voltage rated devices for directional switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high-frequency SiC MOSFETs are used for PWM switching, then switching losses are reduced and performance is improved, but overvoltage stress occurs on switching devices due to latency differences, reducing device lifetime
Solution Approach 1:
The patent applies preliminary action by extending the deadtime of high-frequency SiC MOSFETs to match the commutation time of low-frequency IGBTs before switching occurs. This pre-synchronization of switching times prevents overvoltage stress that would otherwise occur due to latency differences between device types, thereby maintaining device reliability while preserving the low switching loss benefits of SiC MOSFETs
Solution Approach 2:
The patent changes the deadtime parameter of high-frequency switching devices to equal the commutation time of low-frequency devices. This parameter adjustment synchronizes the switching behavior of mixed device types, preventing excessive voltage stress and ensuring reliable operation while maintaining the performance advantages of high-frequency switching
2Ease of manufacture
If mixed high-frequency and low-frequency switching devices are used, then cost is reduced by using lower frequency devices for directional switching, but latency differences cause overvoltage stress and device failure
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing the switching times of mixed device types through deadtime extension. This ensures that high-frequency SiC MOSFETs and low-frequency IGBTs switch in coordination, preventing overvoltage stress and device failure while maintaining the cost benefits of using mixed device types
Solution Approach 2:
The patent modifies the deadtime parameter of high-frequency devices to match the commutation characteristics of low-frequency devices. This parameter change harmonizes the switching behavior of heterogeneous devices, enabling reliable operation of cost-effective mixed device configurations
3Reliability
If all switching devices are turned off simultaneously during fault conditions, then system protection is achieved, but all switching latencies occur at the same time causing excessive voltage stress
Solution Approach 1:
The patent applies preliminary action by pre-coordinating the turn-off timing of all switching devices through extended deadtime. This synchronization ensures that devices turn off in a coordinated manner rather than simultaneously, preventing the accumulation of switching latencies that would cause excessive voltage stress during fault conditions while maintaining system protection
4Reliability
If higher level inverters are used, then harmonics are reduced and voltage stress on devices is reduced, but complexity and cost increase making them difficult to implement
Solution Approach 1:
The patent applies local quality by assigning different device types to different functional roles within the inverter - using high-frequency SiC MOSFETs for PWM switching where fast switching is critical and low-frequency IGBTs for directional switching where cost-effectiveness is prioritized. This localized optimization achieves multi-level inverter benefits with reduced complexity compared to uniform high-level designs
Data Source
AI summary
Provided is a novel multi-level inverter with mixed device types and methods of controlling same. This novel multi-level inverter topology and control method allows the use of high frequency switching devices for controlled PWM switching, while also using lower frequency switching devices for directional switches. This combination of high frequency PWM switching devices with low frequency directional switching devices allows a cost reduction without a significant performance degradation.