Mixed Digital-Analog Memory for Secure Neural Network Storage
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Solution Overview
Problem
Non-volatile memory devices used in neural networks are vulnerable to hacking and reverse engineering, as hackers can easily probe and duplicate the weights stored in these devices, posing a significant threat to the security and integrity of the data.
Innovation Solution
A mixed digital-analog memory device is developed, featuring a matrix of memory cells with separate control circuits for digital and analog modes, allowing for secure storage and computation by encrypting data using a pre-generated public key and storing it in different portions of the memory cells, with the most significant bits in digital mode and least significant bits in analog mode, and enabling secure neural network computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If data is stored in non-volatile memory devices for neural networks, then the weights and models can be retained after power off, but the stored data becomes vulnerable to hacking and reverse engineering
Solution Approach 1:
The memory device is divided into multiple independent memory cells arranged in a matrix, where each cell stores individual weight values. This segmentation prevents hackers from easily probing and duplicating the entire neural network model at once, as the data is distributed across many isolated storage units rather than concentrated in a single accessible location.
Solution Approach 2:
Different portions of the memory device utilize different storage modes (digital vs. analog) with distinct characteristics. The digital mode provides high precision for significant bits while the analog mode provides density for less significant bits. This local differentiation in storage quality makes reverse engineering more difficult while optimizing overall security and efficiency.
2Reliability
If separate control circuits are added for digital and analog modes, then data security and computation capability are improved, but device complexity increases
Solution Approach 1:
The memory device incorporates multiple control circuits (first bit-line control circuit for digital mode, second bit-line control circuit for analog mode) that can operate on the same memory cell array. This multi-functionality allows the single memory device to provide both secure digital storage and efficient analog computation capabilities, improving reliability without requiring completely separate hardware systems.
Solution Approach 2:
The patent combines digital and analog storage capabilities within a single memory device structure, merging the functions of what could have been separate systems. The first and second bit-line control circuits are integrated into the same memory array, allowing unified management of both storage modes while maintaining their distinct operational characteristics for security and computation.
3Measurement precision
If all bits are stored in digital mode, then data precision is maximized, but chip size and cost increase
Solution Approach 1:
Instead of storing all bits in high-precision digital mode, the patent applies partial digital storage only to the most significant bits that require high precision. The less significant bits are stored in analog mode, which is sufficient for their lower precision requirements. This partial application of digital storage optimizes chip size while maintaining overall data accuracy.
Solution Approach 2:
Different portions of the stored data receive different storage qualities based on their significance. The most significant bits are stored in digital mode with high precision, while the least significant bits are stored in analog mode with lower precision. This local differentiation in storage quality reduces overall chip size while maintaining sufficient precision for neural network operations.
Data Source
AI summary
A non-volatile memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines extended in a row direction, and a plurality of bit lines extended in a column direction. Each of the memory cells is coupled to one of the word lines and one of the bit lines. The memory device further includes a word-line control circuit coupled to and configured to control the word lines, a first bit-line control circuit configured to control the bit lines and sense the memory cells in a digital mode, and a second bit-line control circuit configured to bias the bit lines and sense the memory cells in an analog mode. The first bit-line control circuit is coupled to a first end of each of the bit lines. The second bit-line control circuit is coupled to a second end of each of the bit lines.