Mixed-Domain FFT LDPC Decoding for Lower-Complexity Error Correction
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Solution Overview
Problem
Current LDPC decoders face inefficiencies and inaccuracies in error correction and detection, particularly in non-binary systems, due to complexity and sensitivity to finite precision.
Innovation Solution
A mixed domain FFT-based non-binary LDPC decoder that performs operations in both the log domain and probability domain, utilizing a message processing circuit for iterative layer decoding, including summation, shifting, and subtraction, and a check node calculation circuit with FFT operations, reducing complexity and improving error performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional non-binary LDPC decoders perform operations in the probability domain, then error correction accuracy is improved, but hardware complexity increases due to required multipliers
Solution Approach 1:
The patent transforms the computational domain by applying logarithmic transformation to convert probability domain operations into log domain operations. This parameter change allows multiplication operations to be replaced with addition operations, significantly reducing hardware complexity while maintaining error correction accuracy. The log domain representation changes the mathematical parameters of the computation without losing information.
Solution Approach 2:
The patent substitutes complex multiplier circuits with simpler adder circuits by operating in the log domain instead of the probability domain. This mechanical substitution replaces expensive hardware components (multipliers) with cheaper components (adders), achieving the same functional goal with reduced hardware complexity and lower cost.
2Device complexity
If LDPC decoders operate in the log domain, then hardware complexity is reduced by using adders instead of multipliers, but error correction performance deteriorates
Solution Approach 1:
The patent introduces an intermediary transformation process that converts between log domain and probability domain as needed. The intermediary includes forward transformation (log domain to probability domain) for check node calculations and backward transformation (probability domain to log domain) for variable node updates. This intermediary mechanism allows the system to leverage the simplicity of log domain arithmetic while maintaining the accuracy benefits of probability domain operations when necessary.
Solution Approach 2:
The patent segments the decoding process into distinct stages operating in different domains: variable node processing operates in the log domain for simplicity, while check node processing operates in the probability domain for accuracy. This segmentation allows each part of the system to operate in the most suitable domain for its specific function, optimizing both hardware complexity and error correction performance.
3Reliability
If multiple check nodes perform parity checks in iterative decoding, then error detection and correction capability is improved, but processing time increases
Solution Approach 1:
The patent implements periodic iterative decoding where multiple check nodes perform parity checks in repeated cycles. Each iteration refines the error correction progressively, with the periodic repetition allowing the system to achieve high reliability through cumulative processing. The periodic action enables thorough error correction while allowing parallel operations within each iteration to minimize overall processing time.
Solution Approach 2:
The patent performs preliminary error detection and correction in early iterations before full decoding is complete. By identifying and correcting obvious errors in preliminary passes, the system reduces the processing burden in subsequent iterations, thereby reducing total processing time while maintaining high error correction capability.
Data Source
AI summary
Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding data in a mixed domain FFT-based non-binary LDPC decoder. For example, in one embodiment an apparatus includes a message processing circuit operable to process variable node messages and check node messages in a log domain, and a check node calculation circuit in the low density parity check decoder operable to perform a Fast Fourier Transform-based check node calculation in a real domain. The message processing circuit and the check node calculation circuit perform iterative layer decoding.