Fabricating Mixed FET Types via Segmented Active Regions
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Solution Overview
Problem
The existing processes for fabricating field effect transistors with different structures, such as planar and fin types, often result in structural degradation of fins and contamination, leading to deteriorated characteristics and failures in semiconductor memory devices due to complex fabrication processes and thermal budgets.
Innovation Solution
A method involving the deposition of a first conductive layer over active regions, patterning to form mold structures and gates, with additional mask structures to preserve the integrity of fins, and the use of a conductive film to adjust threshold voltage, along with buffer layers and trench isolation to prevent contamination and structural damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional fabrication processes are used to form multiple FET types simultaneously, then manufacturing complexity increases, but fin structural integrity deteriorates due to etching and oxidation damage
Solution Approach 1:
The substrate is divided into distinct first and second active regions with different fin structures. The first active region contains fins of a first width while the second active region contains fins of a second width. This segmentation allows each region to be optimized independently while being fabricated simultaneously, resolving the contradiction between productivity and manufacturing precision.
Solution Approach 2:
Different gate oxide layer thicknesses are formed in different active regions to match the local fin width requirements. The first gate oxide layer has a first thickness for the first active region, while the second gate oxide layer has a second thickness for the second active region. This local quality adjustment ensures optimal device characteristics for each region without compromising fin structural integrity during fabrication.
2Reliability
If high temperature oxidation processes are performed for subsequent structures, then gate oxide formation is improved, but thermal budget creates contamination and degradation
Solution Approach 1:
Gate oxide layers are formed on the fins before the fin etching process. This preliminary action ensures that the gate oxide is already in place and protected when subsequent high temperature oxidation processes are performed for other structures, preventing thermal budget contamination and degradation of the gate oxide quality.
Solution Approach 2:
The gate oxide layer acts as a protective cushion for the fin structure during subsequent high temperature processing steps. By forming the gate oxide beforehand, the fin structure is shielded from thermal budget-induced contamination and degradation that would otherwise occur during later oxidation processes.
3Adaptability or versatility
If first gate conductive layer and oxide are formed in first active region, then planar MOSFET is created, but fin width is excessively reduced during removal processes
Solution Approach 1:
Different gate oxide thicknesses are used in different active regions to compensate for the different fin widths. The first gate oxide layer has a first thickness for the first active region with wider fins, while the second gate oxide layer has a second thickness for the second active region with narrower fins. This local quality adjustment ensures that the electrical characteristics are optimized for each region's specific fin geometry.
Solution Approach 2:
The gate oxide thickness parameter is changed between different active regions to match the local fin width. By adjusting this critical parameter, the invention compensates for the fin width reduction that occurs during removal processes, maintaining proper device characteristics across different MOSFET types.
4Reliability
If second gate conductive layer is formed with metal, then device performance is improved, but first gate conductive layer is contaminated
Solution Approach 1:
The first gate conductive layer is formed in the first active region before the second gate conductive layer is formed in the second active region. This preliminary formation ensures that the first gate conductive layer is already in place and protected during the metal deposition process for the second gate, preventing contamination while allowing the use of metal for improved device performance.
Solution Approach 2:
The gate conductive layer formation is segmented into separate steps for different active regions. The first gate conductive layer is formed and established in the first active region before metal deposition for the second gate occurs in the second active region. This segmentation prevents metal contamination of the first gate conductive layer while still enabling high-performance metal gates where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the simultaneous formation of multiple field effect transistors with high integrity, preventing structural degradation and contamination, thereby improving the reliability and performance of MOSFETs in semiconductor memory devices.
Implementation Method 1
a conductive film is formed between the gate dielectric material and the second conductive layer to adjust a threshold voltage of the second FET
Implementation Method 2
a first conductive layer is deposited over first and second active regions of a semiconductor substrate
Implementation Method 3
a gate dielectric material is formed on the fins
Data Source
AI summary
For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.