Mixed Fin Transistor Layout for Odd-Fin GAA Cell Compression
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Solution Overview
Problem
Conventional methods for forming gate-all-around (GAA) FETs face challenges in scaling the channel, requiring a balance of competing parameters that often lead to increased width and thickness, resulting in electrical shorts, reduced channel stability, and performance issues, while existing processes for forming crossbar-shaped or H-shaped fins are not optimized for applications with odd numbers of straight fins.
Innovation Solution
A method and structure that include two-dimensional fins and an odd number of one-dimensional fins, where the one-dimensional fins have a different critical dimension than the two-dimensional fins, allowing for increased cell compression and efficient formation of crossbar-shaped or H-shaped fins with an odd number of straight fins, using a process that forms mandrels, deposits and etches spacer materials to define the fin structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional methods are used to form gate-all-around FETs with scaled channels, then transistor density is improved, but electrical shorts and reduced channel stability occur
Solution Approach 1:
The channel is divided into multiple stacked nanosheets (e.g., 3-7 nanosheets per stack) rather than using a single thick channel. This segmentation allows each nanosheet to be independently controlled by the gate, improving stability while maintaining high density. The gate wraps around all sides of each nanosheet stack, providing comprehensive control over current flow through the segmented channel structure.
Solution Approach 2:
The invention transitions from planar 2D channels to three-dimensional stacked nanosheet channels with gate-all-around configuration. The gate structure extends vertically to surround all sides of the stacked nanosheets, adding dimensional control that prevents electrical shorts while maintaining scaled channel dimensions. This 3D configuration allows independent control of each nanosheet layer.
2Manufacturing precision
If crossbar-shaped fins are formed using existing processes, then fin structure performance is improved, but the process is not optimized for odd numbers of straight fins
Solution Approach 1:
The process uses different spacer materials with different etch selectivities to define different fin regions. First spacer material defines crossbar-shaped fin regions, while second spacer material defines straight fin regions. This local differentiation allows the same process flow to create both crossbar fins (for even positions) and straight fins (for odd positions) with precise control over their respective geometries.
Solution Approach 2:
The invention changes the spacer material parameter to accommodate different fin configurations. By using two different spacer materials with different properties (etch selectivity, deposition characteristics), the process can be adapted to form both crossbar-shaped fins and straight fins within the same cell structure, enabling support for odd numbers of fins while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance by increasing cell compression and enabling efficient formation of crossbar-shaped or H-shaped fins with an odd number of straight fins, addressing the limitations of conventional processes and improving scaling and stability of GAA FETs.
Implementation Method 1
depositing and anisotropically etching back the first spacer material to form first and second spacers in and around the first and second mandrels
Implementation Method 2
conformally depositing and anisotropically etching back second spacer material around the first and second spacers and in the pitch gap region
Data Source
AI summary
A method of forming a transistor structure is provided. The method includes forming on a substrate first and second mandrels for forming two-dimensional (2D) transistor fin elements defining a pitch gap region, depositing and anisotropically etching back the first spacer material to form first and second spacers in and around the first and second mandrels, respectively, conformally depositing and anisotropically etching back second spacer material around the first and second spacers and in the pitch gap region to define space for forming an odd number of one-dimensional (1D) transistor fin elements in the pitch gap region and depositing and anisotropically etching back the first spacer material in the space with enough cycles to fill the space to form a third spacer.


