Mixed GAA and Planar Semiconductor Layout for Thick I/O Gate Oxides
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Solution Overview
Problem
Vertically stacked gate-all-around (GAA) horizontal nanowire and nanosheet devices face limitations due to the restricted thickness of the gate dielectric layer, making them unsuitable for applications requiring thicker dielectric layers, such as input/output (I/O) functions, where improved gate dielectric thickness is needed.
Innovation Solution
The integration of GAA NW and GAA NS devices with planar devices on the same substrate, where GAA devices are placed in the core area for low-power and high-speed circuits, and planar devices are used in the I/O area for implementing I/O circuits, with GAA NS devices having a wider channel width than GAA NW devices to differentiate performance, and planar devices having a thicker gate dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GAA NW and GAA NS devices are used, then gate controllability and scalability are improved, but gate dielectric layer thickness is limited
Solution Approach 1:
The patent divides the semiconductor device into two distinct types: GAA devices for core logic circuits and planar devices for I/O circuits. This segmentation allows each device type to be optimized independently - GAA devices achieve superior gate controllability with thin dielectric layers, while planar devices provide the necessary thick gate dielectric layers for I/O applications, thereby resolving the contradiction between improved gate controllability and limited dielectric thickness.
Solution Approach 2:
The patent applies different device structures to different functional areas of the semiconductor chip. Core logic circuits use GAA devices with optimized thin gate dielectric for high performance, while I/O circuits use planar devices with thick gate dielectric for reliability and noise immunity. This local quality approach allows each region to have the specific dielectric thickness required for its function, resolving the universal limitation of GAA devices.
2Length of stationary object
If planar devices are used, then thick gate dielectric layer is achieved, but gate controllability and scalability are reduced
Solution Approach 1:
The patent segments the chip into distinct functional regions using different device architectures. Planar devices with thick gate dielectric are deployed specifically in I/O areas where noise immunity and isolation are critical, while GAA devices with excellent gate controllability handle core logic functions. This segmentation ensures that planar devices' thick dielectric is applied only where needed, maintaining gate controllability in performance-critical areas.
Solution Approach 2:
The patent implements local quality by tailoring the device structure to the specific functional requirements of each circuit region. I/O circuits receive planar devices with thick gate dielectric for enhanced noise immunity and isolation, while core logic circuits utilize GAA devices with superior gate controllability. This localized optimization resolves the contradiction by applying thick dielectric only where it provides benefit without compromising overall gate controllability.
3Ease of manufacture
If a single device type is used throughout the IC, then manufacturing is simplified, but design flexibility and performance optimization are limited
Solution Approach 1:
The patent segments the semiconductor device into multiple functional blocks, each utilizing the most appropriate device type for its specific function. This segmentation enables design flexibility - core logic blocks use high-performance GAA devices while I/O blocks use robust planar devices with thick dielectric. The segmentation is implemented in a way that allows separate optimization of each block while maintaining overall manufacturing feasibility through standardized process flows.
Solution Approach 2:
The patent creates a universal semiconductor manufacturing platform that can produce both GAA and planar devices using compatible fabrication processes. This multi-functionality approach allows the same manufacturing line to produce different device types for different functional blocks, maintaining ease of manufacture while achieving design flexibility. The unified process architecture enables mixed-device integration without requiring entirely separate manufacturing lines.
Data Source
AI summary
An integrated circuit includes a substrate and a first active region and a second active region extending lengthwise along a first direction over the substrate. The first active region includes vertically stacked multiple first channels, and the second active region includes vertically stacked multiple second channels. The integrated circuit further includes a dielectric gate extending between the first active region and the second active region and extending lengthwise along a second direction perpendicular to the first direction, and a first metal gate structure disposed over the first active region and a second metal gate structure disposed over the second active region. The first metal gate structure and the second metal gate structure extend lengthwise along the second direction. The first channels have a first width along the second direction and the second channels have a second width along the second direction. The second width is less than the first width.