Mixed Gate CMOS Single Poly Deposition
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Solution Overview
Problem
The challenge lies in effectively combining metal gate and polysilicon gate devices in CMOS structures, as their differing processing requirements complicate fabrication, especially in deeply submicron generations, where traditional methods struggle to maintain performance enhancements and alignment tolerances, leading to difficulties in achieving tight device separations and cost-effective manufacturing.
Innovation Solution
A method is introduced for processing mixed gate CMOS structures by implementing a high-k gate insulator for metal gate devices and an oxide gate insulator for polysilicon gate devices, using a protective material to prevent damage during oxidation, and employing a single block-level mask for defining both types of gates, allowing for denser circuit designs and cost savings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional separate processing methods are used for metal gate and polysilicon gate devices, then each device type can be optimized independently, but the fabrication process becomes complex with multiple masking steps and alignment tolerances issues
Solution Approach 1:
The patent combines the processing of metal gate and polysilicon gate devices into a single integrated fabrication flow. Both device types share common processing steps including gate insulator formation, protective material deposition, and single mask alignment, eliminating the need for separate processing sequences and reducing overall process complexity.
Solution Approach 2:
The fabrication method creates a universal processing approach that handles both metal gate and polysilicon gate devices simultaneously. The gate insulator formation, protective material application, and mask alignment steps serve both device types, allowing the same process sequence to produce optimized performance for each device type without requiring dedicated processing lines.
2Manufacturing precision
If multiple masking steps are used to define different gate regions, then precise alignment can be achieved, but manufacturing cost increases and productivity decreases
Solution Approach 1:
The patent merges the definition of metal gate and polysilicon gate regions into a single mask step. The mask simultaneously defines both gate types during one exposure and development cycle, eliminating multiple sequential masking operations. This reduces the number of process steps while maintaining precise alignment through a single reference frame.
Solution Approach 2:
The method performs preliminary protective material deposition over the entire wafer before mask application. This preliminary action ensures that both metal gate and polysilicon gate regions are protected uniformly, and the subsequent single mask step can define both gate types without requiring intermediate protective measures between masking operations.
3Area of moving object
If device dimensions are scaled down to deeply submicron generations, then circuit density increases, but maintaining performance enhancements becomes more difficult
Solution Approach 1:
The patent applies local quality by providing different gate insulator structures tailored to each device type's specific performance requirements. Metal gate devices receive gate insulators optimized for their electrical characteristics, while polysilicon gate devices receive gate insulators optimized for their requirements. This localized optimization ensures each device type maintains peak performance despite overall scaling to deeply submicron dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of CMOS structures with improved performance and tighter device separations, reducing the number of masking steps and maintaining performance enhancements in shrinking device dimensions, while simplifying the manufacturing process and achieving cost savings.
Implementation Method 1
the implementation of a second gate insulator by performing an oxidation
Data Source
AI summary
A method for fabricating metal gate and polysilicon gate FET devices on the same chip is disclosed. The method avoids the use of two separate masks during gate stack fabrication of the differing gates. By using a single mask, tighter NFET to PFET distances can be achieved, and the fabrication process is simplified. After blanket disposing layers for the fabrication of the metal gate stack, a covering protective material layer is formed, again in blanket fashion. A block level mask is used to clear the surface for the gate insulator formation in the poly gate device regions. During oxidation, which forms the gate dielectric for the poly gate devices, the protective material prevents damage of the metal gate device regions. Following oxidation, a single common polysilicon cover is disposed in blanket manner for continuing the fabrication of the gate stacks. The protective material is selected in such a way to be either easily removable upon oxidation, or to be conductive upon oxidation. In this latter case the oxidized protective material is incorporated into the metal gate stack, which incorporation results in a novel CMOS structure.