Mixed Gate-Design FETs for Integrated Circuit Performance
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Solution Overview
Problem
There is a challenge in developing semiconductor integrated circuits that balance high performance, low power consumption, and low variation in transistor threshold voltages as device integration increases, making it difficult to achieve all three criteria simultaneously.
Innovation Solution
The integration of multiple field effect transistor designs on the same chip, where pi-gate transistors with higher gate capacitance and lower leakage current are used in back-end-of-line-loaded unit circuits, and non-pi-gate transistors with lower gate capacitance and higher switching speeds are used in gate-loaded unit circuits, optimizing capacitance and leakage current based on circuit type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If line widths are reduced to increase device integration, then device integration increases, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent applies different gate design configurations to different transistor groups based on their specific circuit requirements. First group transistors use a first gate design while second group transistors use a second gate design, allowing each group to be optimized for its specific function rather than using a uniform design across all devices.
Solution Approach 2:
The patent modifies physical parameters of the gate structures, including gate electrode bottom surface positions relative to the substrate, gate capacitance values, and channel conduction widths. These parameter variations enable transistors to be tuned for specific performance characteristics such as low leakage current or high switching speed.
2Object-generated harmful factors
If pi-gate transistors with higher gate capacitance are used, then leakage current decreases, but gate capacitance increases
Solution Approach 1:
Pi-gate transistors with higher gate capacitance and lower leakage current are selectively deployed in back-end-of-line-loaded unit circuits where low leakage is critical, while non-pi-gate transistors with lower gate capacitance are used in gate-loaded unit circuits where switching speed is more important.
3Speed
If non-pi-gate transistors with lower gate capacitance are used, then switching speed increases, but leakage current increases
Solution Approach 1:
Non-pi-gate transistors with lower gate capacitance and higher switching speeds are selectively deployed in gate-loaded unit circuits where fast switching is critical, while accepting higher leakage current characteristics in these specific locations.
4Productivity
If multiple transistor designs are integrated on the same chip, then circuit performance is optimized, but device complexity increases
Solution Approach 1:
The chip is segmented into different unit circuit types (back-end-of-line-loaded and gate-loaded circuits), with each segment using the transistor design best suited for its specific functional requirements. This segmentation allows performance optimization without requiring complete redesign of all circuits.
Data Source
AI summary
An integrated circuit chip includes a semiconductor substrate, a first back-end-of-line unit circuit that includes a first group of field effect transistors, a second gate-loaded unit circuit that includes a second group of field effect transistors. The first group of field effect transistors includes a first transistor and the second group of field effect transistors includes a second transistor. A bottom surface of a gate electrode of the first transistor extends closer to a bottom surface of the semiconductor substrate than does a bottom surface of a gate electrode of the second transistor.