Integrated Circuit Fabrication with Mixed Gate Heights
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Solution Overview
Problem
The reduction in semiconductor device dimensions leads to increased leakage current due to thin gate insulation layers, and the use of high-k materials can cause Fermi-level pinning, affecting device performance, especially in high-voltage devices where specific gate insulating layer thickness is crucial to prevent breakdown under high operation voltages.
Innovation Solution
A method for fabricating an integrated circuit that integrates high-k/metal gate semiconductor devices with poly-silicon semiconductor devices by forming stacked structures with different gate insulating layers and gates, allowing for the use of a metal gate in conjunction with poly-silicon gates of varying thicknesses, and includes steps like forming dielectric material layers, patterning, and planarizing to expose the top surfaces, thereby simplifying the process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the gate insulation layer thickness is reduced to accommodate smaller device dimensions, then the device size is reduced, but leakage current increases
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate insulation layer by using high-k materials (such as HfO2, ZrO2, or their alloys) instead of traditional silicon oxide. This allows maintaining a thin physical thickness for small device dimensions while achieving higher effective insulation through the increased dielectric constant, thereby reducing leakage current despite the reduced thickness
Solution Approach 2:
The patent employs composite gate structures combining multiple materials: a high-k dielectric layer (such as HfO2-ZrO2 alloy) combined with a metal gate layer (such as TiN, TaN, or tungsten). This composite structure provides both the high dielectric constant needed for low leakage and the appropriate electrical characteristics for gate operation
2Object-generated harmful factors
If high-k material is used to reduce leakage current, then leakage current is reduced, but Fermi-level pinning occurs causing threshold voltage increase and performance degradation
Solution Approach 1:
The patent introduces a metal gate layer as an intermediary between the high-k dielectric and the semiconductor channel. This metal gate acts as a buffer that prevents direct interaction between the high-k material and the channel, avoiding Fermi-level pinning while still benefiting from the high dielectric constant for leakage reduction
Solution Approach 2:
The composite high-k/metal gate structure combines the advantages of both materials: the high-k dielectric provides high breakdown voltage and low leakage, while the metal gate provides appropriate work function and prevents Fermi-level pinning, together delivering improved device performance
3Reliability
If metal gate is used to avoid Fermi-level pinning, then threshold voltage control is improved, but process complexity increases when integrating with poly-silicon devices
Solution Approach 1:
The patent divides the semiconductor device into separate regions: a first region with poly-silicon gate and a second region with high-k/metal gate. This segmentation allows each region to be optimized independently while sharing common process steps, reducing overall integration complexity
Solution Approach 2:
The patent uses a stacked structure where the high-k dielectric and metal gate are formed in layers above the semiconductor substrate. This vertical stacking allows simultaneous formation of different gate types in different regions through selective patterning, simplifying the integration process
4Reliability
If high-k/metal gate structure is formed with multiple layers, then device performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the formation of the high-k/metal gate structure with existing CMOS fabrication processes. The high-k dielectric is deposited using standard ALD or CVD techniques, and the metal gate is formed using conventional sputtering or evaporation, integrating these advanced structures into established manufacturing workflows
Solution Approach 2:
The patent performs preliminary formation of the high-k dielectric layer and metal gate layer before final gate patterning. This preliminary action allows the complex multi-layer structure to be established early, simplifying subsequent processing steps and enabling better process control
Data Source
AI summary
A method for fabricating an integrated circuit includes the following steps of: providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure, wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing.