Mixed-Gate TFT Pixel Layout for Narrow-Bezel High-Resolution Displays
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Solution Overview
Problem
High-resolution flat panel display devices face challenges in accommodating the area for the scan driver circuit and thin-film transistors as the number of pixels increases, leading to larger transistor sizes that are difficult to fit within the display device.
Innovation Solution
The implementation of a display device design that reduces the width of the scan driver circuit and switching transistors by using a top gate structure for driving transistors and a bottom gate structure for switching transistors, with indium-gallium-zinc oxide or indium-tin-zinc oxide active layers, allowing for a more compact layout without increasing the number of manufacturing masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels is increased to achieve high resolution, then the display resolution is improved, but the area required for scan driver circuit and thin-film transistors increases making it difficult to accommodate within the display device
Solution Approach 1:
The patent divides the transistor structure into two distinct types: driving transistors with top gate configuration and switching transistors with bottom gate configuration. This segmentation allows each transistor type to be optimized independently for its specific function, enabling smaller overall transistor areas while maintaining high display resolution.
Solution Approach 2:
Different gate structures are applied to different transistor types based on their functional requirements. Driving transistors use top gate structure optimized for driving OLED pixels, while switching transistors use bottom gate structure optimized for switching operations. This local differentiation of structure quality enables compact design without compromising performance.
2Measurement precision
If the transistor width is reduced to accommodate more pixels, then the pixel density is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent extracts the gate electrode from its conventional position above the active layer and places it below the active layer for switching transistors. This extraction of the gate structure to a different spatial position simplifies the overall transistor design and enables compact layout while maintaining manufacturability through standard TFT fabrication processes.
Solution Approach 2:
The patent transitions from the conventional top-gate configuration to bottom-gate configuration for switching transistors, effectively changing the dimensional arrangement of the gate electrode. This dimensional change allows for reduced transistor area while maintaining electrical performance and compatibility with existing manufacturing processes.
3Area of stationary object
If different gate structures are used for driving and switching transistors, then the transistor area is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The patent changes the positional parameter of the gate electrode (from above to below the active layer) for switching transistors while keeping the driving transistor structure conventional. This parameter change enables area reduction and is achieved through modifications in the existing TFT fabrication process sequence, maintaining process economics without requiring entirely new manufacturing techniques.
Data Source
AI summary
A display device includes a plurality of pixels respectively coupled to scan lines and data lines intersecting the scan lines, wherein at least some of the pixels includes a driving transistor including a substrate, a first insulating layer disposed on the substrate, a first active layer disposed on the first insulating layer, a first gate electrode disposed on the first active layer, and a first source electrode and a first drain electrode electrically connected to the first active layer, the first drain electrode being spaced apart from the first source electrode by a first distance, and a switching transistor including a second gate electrode disposed between the substrate and the first insulating layer, a second active layer disposed on the same layer as the first active layer, and a second source electrode and a second drain electrode electrically connected to the second active layer, the second drain electrode being spaced apart from the second source electrode by a second distance different from the first distance.