Mixed-Height Nanoribbon Cell Rows for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuit design, maximizing space while minimizing parasitic effects becomes challenging as devices and unit cells shrink, leading to inefficiencies in transistor layout and increased parasitic capacitance, which degrades performance.
Innovation Solution
The approach involves forming rows of cells with varying heights and nanoribbon widths, where some rows have a height at least 3 nm shorter than others, allowing for differently sized semiconductor bodies and optimized gate area usage, thereby reducing wasted space and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard unit cell libraries with fixed transistor configurations are used, then design simplicity is maintained, but space utilization efficiency deteriorates and parasitic effects increase
Solution Approach 1:
The patent segments the unit cell library into multiple cell types with different heights (first cell type with height H1, second cell type with height H2) and different nanoribbon widths. This segmentation allows selective placement of appropriately sized cells to match the specific transistor requirements, optimizing space utilization while maintaining design flexibility through standardized cell modules.
Solution Approach 2:
The patent applies local quality by assigning different cell characteristics (height, nanoribbon width) to different locations in the circuit layout based on specific functional requirements. Each cell type is optimized for its particular application, with taller cells used where larger transistor areas are needed and shorter cells used where compact layouts are prioritized, thereby optimizing overall space utilization.
2Area of stationary object
If device sizes are reduced to maximize density, then area efficiency improves, but parasitic capacitance increases and performance degrades
Solution Approach 1:
The patent changes the parameter of cell height to optimize the balance between area efficiency and parasitic capacitance. By providing cell types with different heights (H1, H2) and different nanoribbon widths, the design can select appropriate parameters for each location, ensuring that devices are sized appropriately rather than uniformly miniaturized, thus reducing parasitic effects while maintaining area efficiency.
3Manufacturing precision
If uniform cell heights are used across all rows, then manufacturing consistency is improved, but gate area optimization deteriorates due to wasted space
Solution Approach 1:
The patent segments the cell population into distinct types with different heights, each type being manufactured with consistent dimensions. This segmentation allows manufacturing processes to maintain precision for each cell type while the overall circuit benefits from optimized gate area utilization through selective placement of appropriately sized cells.
Solution Approach 2:
The patent creates a universal cell library where different cell types can be used across multiple locations depending on requirements. Each cell type serves multiple functions (different transistor counts, different area requirements) while maintaining manufacturing consistency through standardized fabrication processes for each cell type.
4Productivity
If larger nanoribbon widths are used, then transistor performance improves, but area consumption increases and density decreases
Solution Approach 1:
The patent applies local quality by varying nanoribbon widths at different locations based on performance requirements. Critical path transistors or high-performance requirements locations receive larger nanoribbon widths for improved performance, while non-critical locations use smaller nanoribbon widths to minimize area consumption, optimizing the overall density-performance balance.
Data Source
Figure 1A
Figure 1B
Figure 2A~2B
AI summary
Techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. An integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. Additionally, the various rows of cells contain semiconductor nanoribbons having different widths between different rows. For example, any number of first rows of cells can each have a first height (h1) and any number of second rows can each have a second height (h2) that is smaller than the first height. The first rows of cells may include transistors with semiconductor nanoribbons having a first width (w1) and the second rows of cells may include transistors with semiconductor nanoribbons having a second width (w2) smaller than the first width. In some cases, any of the first rows of cells may also include transistors with semiconductor nanoribbons having the second width.