Mixed-Height Cell Power-Line Layout for Dense Semiconductor Integration
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration and improved electrical characteristics, particularly in meeting demands for high reliability, high speed, and multi-functionality.
Innovation Solution
A semiconductor device is designed with a substrate that includes NMOSFET and PMOSFET regions, featuring active patterns, gate electrodes, source/drain patterns, active contacts, gate contacts, and a metal layer. The device incorporates a mixed height cell structure with varying line tracks and lower lines to enhance integration and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are made more integrated to meet high integration demands, then device functionality and density improve, but device complexity increases
Solution Approach 1:
The substrate is divided into distinct first and second regions with different active patterns (first and second active patterns), allowing independent optimization of each segment while achieving overall high integration. The gate electrodes are also segmented into first and second gate electrodes that can be independently controlled.
Solution Approach 2:
The first and second active patterns are configured to enable multi-functionality within the integrated device structure. The shared gate electrode structure serves multiple functions by controlling both active patterns, while the differential configuration allows for various logic operations.
2Area of stationary object
If device integration is increased, then area required is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The first and second active patterns are positioned at equivalent heights relative to the substrate surface, creating an equipotential configuration that simplifies manufacturing alignment. The gate electrodes are formed at a uniform height above both active patterns, ensuring consistent electrical characteristics and reducing alignment variability.
3Area of stationary object
If device integration is increased, then device area is reduced, but electrical characteristics may deteriorate
Solution Approach 1:
Different active patterns are provided in different regions of the substrate, allowing each region to be optimized for specific electrical characteristics. The first active pattern in the first region and the second active pattern in the second region can have different dimensions and properties tailored to their functional requirements, maintaining high electrical performance in the compact integrated structure.
Data Source
AI summary
Disclosed is a semiconductor device comprising a mixed height cell on a substrate, and a first power line and a second power line that run across the mixed height cell. First to third line tracks are defined between the first power line and the second power line. A fourth line track is defined adjacent to the second power line. The second power line is between the third line track and the fourth line track. The mixed height cell includes a plurality of lower lines aligned with the first to fourth line tracks. A cell height of the mixed height cell is about 1.25 times to about 1.5 times a distance between a first point of the first power line and a corresponding second point of the second power line.