Mixed-Height Socket Contacts for High-Bandwidth Signal Integrity
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving higher bandwidth rates between CPUs and memory due to impedance discontinuities caused by traditional socket pins extending through the socket, which limits signal performance and requires costly low-profile power delivery solutions.
Innovation Solution
Implementing an interconnect layer on the socket with mixed-height socket pins, where high-speed pins terminate within the socket and mid-speed and low-speed pins extend through it, reducing impedance discontinuities and enabling wider bandwidth without board-level routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional socket pins extend through the socket, then mechanical strength and structural simplicity are maintained, but impedance discontinuities increase and signal integrity deteriorates
Solution Approach 1:
The socket pins are segmented into two distinct types: high-speed pins that terminate within the socket at the interconnect layer, and mid-speed/low-speed pins that extend through the socket. This segmentation allows each pin type to be optimized for its specific function, with high-speed pins providing short, controlled impedance paths for high-frequency signals while through-pins serve slower signals, thereby resolving the impedance discontinuity issue without requiring complete redesign of all pin structures
Solution Approach 2:
Different regions of the socket are assigned different pin characteristics based on local signal requirements. High-speed signal paths utilize short pins terminating at the interconnect layer with optimized impedance control, while other regions use traditional through-pins. This local differentiation of pin quality allows the socket to simultaneously accommodate both high-speed and lower-speed connections with appropriate structural characteristics for each
2Speed
If socket z-height is reduced to achieve faster bandwidth, then signal transmission speed improves, but power delivery becomes challenging and costly
Solution Approach 1:
Instead of reducing the entire socket z-height uniformly, the invention applies partial action by only shortening the high-speed pins that require fastest signal transmission. The socket maintains its overall height and traditional power delivery structure, while selectively providing short pin paths only where high-speed performance is critical. This avoids the costly and complex low-profile power delivery solutions that would be required if the entire socket were reduced in height
3Adaptability or versatility
If top side connector is added to CPU chip for selective speed scaling, then bandwidth flexibility improves, but manufacturing complexity and testing requirements increase
Solution Approach 1:
Instead of adding complexity to the CPU chip with top-side connectors and heat sink cut-outs, the invention inverts the approach by implementing the mixed-pin architecture within the socket itself. The socket becomes the active component providing selective speed scaling capabilities, while the CPU chip maintains its traditional, simpler structure. This transfers the complexity from the CPU to the socket, achieving the same functional goal of selective speed scaling without modifying the CPU manufacturing process
Data Source
AI summary
A processor package module includes a socket having a first side and a second side, where the second side includes interconnect joints. The socket further includes a root complex and a non-root complex over the first side. An interconnect layer is on the first side of the socket and has one or more levels of routing traces. A first set of socket pins connects the root complex and non-root package to the interconnect layer, where the first set of socket pins terminate at the interconnect layer.