Automated Interconnect Generation in Mixed Language Circuit Design
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Solution Overview
Problem
In electronic design automation, connecting design units in mixed language environments is challenging due to the need for expertise and the introduction of implicit hierarchies, which complicates functional verification and downstream tool operations, especially when design units are already compiled or written in different languages.
Innovation Solution
A design verification tool that generates interconnects between circuit design portions in a mixed language environment by selecting an appropriate interconnect generation technique based on characteristics, allowing automatic interconnect generation during elaboration without modifying the circuit design with code, and modifies verification results to show direct connections, thereby simplifying the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If design units are linked by modifying logical design with code statements (instantiation statements), then design units can be interconnected during elaboration, but implicit hierarchies and dummy hierarchies are introduced that complicate functional verification and downstream tool operations
Solution Approach 1:
The patent extracts the interconnection logic from the design units themselves and places it in the testbench. By removing instantiation statements from design units and replacing them with port declarations, the harmful implicit hierarchies are eliminated while preserving the ability to interconnect design units during elaboration.
Solution Approach 2:
Instead of having design units instantiate each other (bottom-up approach), the patent inverts the approach by having the testbench instantiate and interconnect the design units (top-down approach). This reversal eliminates the need for modification statements within design units and prevents dummy hierarchy creation.
2Adaptability or versatility
If design units are purchased already-compiled or written in different languages, then design flexibility and reusability are improved, but the ability to link design units using traditional instantiation statements becomes impossible
Solution Approach 1:
The patent creates a universal interface mechanism that works across different HDL languages (Verilog, VHDL, SystemVerilog) and different compilation states. By using standardized port declarations and a language-agnostic testbench elaboration process, design units can be interconnected regardless of their source language or compilation status.
Solution Approach 2:
The testbench acts as an intermediary that mediates between design units from different languages and compilation states. It provides a common platform for elaboration and interconnection, translating and coordinating the instantiation of design units regardless of their origin.
3Productivity
If code statements are used to link design units, then interconnection during elaboration is enabled, but functional verification operations, coverage recordation, and downstream tool operations are complicated
Solution Approach 1:
By extracting interconnection logic from design units to the testbench, the patent eliminates the verification complexity caused by implicit hierarchies. The testbench maintains clear visibility of all design unit connections, simplifying functional verification and coverage analysis.
Solution Approach 2:
The testbench automatically manages the interconnection of design units during elaboration without requiring modification statements within the design units themselves. This self-service approach maintains clean design unit interfaces while enabling efficient automated interconnection.
Data Source
AI summary
This application discloses a design verification tool to generate an interconnect between portions of a circuit design in a mixed language environment. The design verification tool can select an interconnect generation technique based on characteristics for the portions of the circuit design and, during elaboration of the circuit design, utilize the selected interconnect generation technique to generate the interconnect. The design verification tool can generate the interconnect without the circuit design including code to identify the selected interconnect generation technique to the design verification tool. The design verification tool can perform functional verification operations on the elaborated circuit design, and modify results of the functional verification operations to remove an intermediate hierarchy utilized to generate the interconnect during elaboration. The modified results can show the portions of the circuit design being directly connected by the interconnect.