Mixed-Language Simulation Code Generation
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Solution Overview
Problem
Mixed-language circuit designs, which use combinations of HDLs like VHDL and Verilog, face inefficiencies in simulation due to differing formats and capabilities, leading to increased simulation complexity and memory requirements.
Innovation Solution
The method involves generating simulation code by modeling datapaths through modules of each HDL using specific dataflow builders, inferring dataflow nets, creating processes, and determining sensitivity, while also creating compatible signal representations and transaction functions to handle signal conversions across language boundaries at compile time, reducing the need for runtime processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If code generation is performed on a per module basis with distinctive representations for Verilog and VHDL modules, then mixed-language simulation can be achieved, but simulation complexity and memory requirements increase
Solution Approach 1:
The patent merges Verilog and VHDL dataflow representations into a unified simulation model. Instead of maintaining separate distinctive representations for each language, the system combines them into a single integrated dataflow graph where signals and modules from both languages are treated uniformly, reducing simulation complexity while preserving mixed-language capability
Solution Approach 2:
The patent creates a universal signal representation that can represent signals from both Verilog and VHDL languages using the same data structure. This universal representation eliminates the need for language-specific signal handling and reduces the complexity of managing multiple representation formats
2Adaptability or versatility
If additional implicit HDL processes are added to handle data type conversion and port connections, then signal propagation across language boundaries is enabled, but memory requirements and simulation complexity increase
Solution Approach 1:
The patent performs data type conversion and port connection mapping during the code generation phase rather than creating implicit processes at simulation runtime. By preprocessing these conversions beforehand, the system eliminates the need for additional runtime memory structures and processes, reducing both simulation complexity and memory requirements
3Ease of operation
If new signals are created during simulation runtime to handle port connections, then Verilog and VHDL modules can be connected, but simulation workload increases
Solution Approach 1:
The patent establishes all port connections and signal mappings during the code generation phase before simulation begins. By pre-configuring the dataflow graph with all necessary connections, the system eliminates runtime signal creation overhead, allowing simulation to proceed efficiently without the performance penalty of dynamic signal generation
Data Source
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AI summary
In one embodiment, a method of generating simulation code of a circuit description having at least one module described in a combination of first and second HDLs is provided. The circuit description is elaborated (401) and a simulation dataflow graph of the circuit description is generated (430). The simulation dataflow graph is generated by modeling a datapath through modules of the first HDL using at least a first dataflow builder (412, 422), and modeling the datapath through modules of the second HDL using at least a second dataflow builder (410, 420). Simulation code, configured to model execution of the design according to the simulation dataflow graph, is generated (440) from the dataflow graph.