Mixed Language Circuit Simulation Clock Event Reduction
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Solution Overview
Problem
Computer-based simulations of circuit designs for integrated circuits (ICs) are inefficient due to the large number of clock events generated, which degrade runtime performance as ICs become larger and more complex, with conventional simulators distributing clock events regardless of the different clocking requirements of various models within a mixed language circuit design.
Innovation Solution
An Electronic Design Automation (EDA) system detects the clock requirements of High-Level Programming Language (HLPL) models within a mixed language circuit design and implements a software-based clock infrastructure that adapts clock information distribution, providing only the necessary clock information to each model, reducing the number of clock events generated and distributed during simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional simulators distribute clock events to all models regardless of their specific clocking requirements, then the simulation can be implemented with a simple uniform distribution mechanism, but the runtime performance degrades due to the large number of clock events generated
Solution Approach 1:
The patent segments the clock event distribution mechanism by model type. It divides models into HDL models that receive detailed clock events and HLPL models that receive simplified clock information. This segmentation allows the system to reduce overall clock event generation while maintaining accuracy where needed, directly improving simulation speed without completely oversimplifying the distribution mechanism.
Solution Approach 2:
The patent applies local quality by providing different qualities of clock information to different models based on their specific requirements. HDL models receive high-quality detailed clock events, while HLPL models receive lower-quality simplified clock information. This localized adaptation of information quality reduces the total number of clock events generated while maintaining simulation accuracy where it matters most.
2Loss of time
If the simulator generates and distributes clock events to all models uniformly, then the implementation remains simple and consistent, but the simulation runtime increases significantly for large and complex IC designs
Solution Approach 1:
The patent introduces dynamics into the clock distribution system by making it adaptive rather than static. The simulator dynamically determines which models are HLPL models and adjusts the clock information distribution accordingly. This dynamic adaptation allows the system to optimize runtime performance for complex designs while maintaining ease of operation through automated detection and configuration.
Solution Approach 2:
The patent changes the parameter of clock information detail level based on model type. Instead of using a fixed parameter for all models, the system varies the clock information parameter - providing detailed clock events for HDL models and simplified clock information for HLPL models. This parameter change directly reduces simulation runtime for large designs while maintaining operational simplicity.
3Measurement precision
If detailed clock events are provided to all models including HLPL models, then the simulation accuracy is maintained, but the number of clock events increases leading to slower simulation performance
Solution Approach 1:
The patent applies partial action by providing only the necessary level of clock information to each model type. HLPL models receive partial clock information (simplified timing data) rather than excessive detailed clock events. This partial provision of information maintains sufficient simulation accuracy for HLPL models while dramatically improving simulation efficiency by reducing the total number of clock events processed.
Solution Approach 2:
The patent segments the simulation accuracy requirements by model type. It recognizes that HDL models require high precision detailed clock events while HLPL models can operate with lower precision simplified clock information. This segmentation of accuracy requirements allows the system to maintain overall simulation accuracy while improving efficiency by not providing excessive detail to models that don't need it.
Data Source
AI summary
Circuit design simulation and clock event reduction may include detecting, using computer hardware, a plurality of models of a circuit design driven by a clock source by parsing the circuit design. The circuit design is a mixed language circuit design including a hardware description language (HDL) model and a high-level programming language (HLPL) model. Using the computer hardware, a clock requirement for the HLPL model for a simulation of the circuit design may be determined. The clock requirement of the HLPL model differs from a clock requirement of the HDL model. Using the computer hardware, an interface of the HLPL model may be modified based on the clock requirement of the HLPL model.