Mixed-Level Floating Gate Memory Cells for Capacitance Variation
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Solution Overview
Problem
As semiconductor memory devices are downscaled, the increased capacitance between adjacent floating gate electrodes leads to variations in threshold voltage, particularly in multilevel memory cells, which complicates the storage of multilevel data and reduces device reliability.
Innovation Solution
A semiconductor integrated circuit device with a memory cell array that mixes first memory cells storing m-level data with second memory cells storing n-level data, where n is greater than m, and a control circuit that writes data to the first memory cell earlier followed by the second memory cell, thereby minimizing the impact of capacitance-induced threshold variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the spacing between adjacent memory cells is narrowed to downscale the device, then the memory device size is reduced, but the capacitance between floating gate electrodes increases causing threshold voltage variation
Solution Approach 1:
The patent segments the memory cell array into different cell types (first memory cells storing m-level data and second memory cells storing n-level data where n>m). By separating multilevel cells and inserting single-level cells between them, the patent divides the continuous array into functional zones that mitigate capacitive coupling effects while maintaining high density.
Solution Approach 2:
The patent introduces first memory cells (storing m-level data) as intermediary elements between second memory cells (storing n-level data). These intermediary cells act as buffers that reduce the direct capacitive coupling between adjacent multilevel cells, thereby stabilizing threshold voltages while allowing narrow spacing.
2Quantity of substance
If multilevel memory cells are used to increase storage capacity, then the memory capacity is increased, but the threshold distribution becomes more sensitive to capacitance variations
Solution Approach 1:
The patent divides the memory cell array into different cell types with different data storage capacities. Second memory cells store n-level data (higher capacity) while first memory cells store m-level data (lower capacity). This segmentation allows high-capacity cells to be separated by lower-capacity cells, reducing capacitive interference and improving threshold distribution control.
Solution Approach 2:
The patent applies different cell configurations to different locations within the memory array. Multilevel cells (second memory cells) are strategically placed and separated by single-level cells (first memory cells), creating local variations in cell structure that optimize both capacity and threshold stability in different regions of the array.
3Measurement precision
If the threshold distribution per data is controlled in a narrow range to store multilevel data, then the data storage precision is improved, but the threshold becomes more susceptible to capacitance effects from adjacent cells
Solution Approach 1:
The patent introduces first memory cells as intermediary elements between second memory cells. These intermediaries reduce the direct capacitive coupling between adjacent multilevel cells, allowing narrow threshold distributions to be maintained without excessive susceptibility to capacitance effects from neighboring cells.
Solution Approach 2:
By segmenting the array into different cell types with different threshold distribution characteristics, the patent creates physical and electrical separation between sensitive multilevel cells. This segmentation reduces the propagation of capacitive effects while preserving the precision of threshold distribution in each cell type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the threshold distribution of second memory cells and increases memory capacity by separating multilevel cells, ensuring reliable read/write operations and preventing threshold variations due to capacitance between floating gate electrodes.
Implementation Method 1
The memory device retains memory by accumulating electric charge in the floating gate electrode
Implementation Method 2
the capacitance between floating gates in adjacent cells increases. Then the threshold of the previously written cell tends to vary because it is more susceptible to the capacitance between floating gate electrodes with its adjacent cell that is subsequently written
Data Source
AI summary
A semiconductor integrated circuit device includes a memory cell array. In the memory cell array, first memory cells of floating gate type are mixed with second memory cells of floating gate type. The second memory cell is sandwiched between the first memory cells. The first memory cells of floating gate type are configured to store m-level data, where m is a natural number of 2 or more. The second memory cells of floating gate type is configured to store n-level data, where n is a natural number greater than m.