Mixed-Level NAND Memory with MLC-to-SLC Data Remapping

Solution Overview

Problem

Existing NAND flash storage systems face challenges in achieving long lifetime endurance while maintaining cost-effectiveness, particularly due to the limited write endurance of Multi-Level Cell (MLC) NAND flash and the superior cost of Single-Level Cell (SLC) NAND flash.

Innovation Solution

A hybrid system combining MLC and SLC NAND flash, where a controller performs data integrity tests and remaps failed data from MLC to SLC NAND flash, ensuring data integrity and extending the system's lifetime by utilizing SLC flash for critical data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If MLC NAND flash is used for storage, then storage capacity and cost-effectiveness are improved, but write endurance and reliability deteriorate

Engineering Contradiction:

Improvestorage capacityVSAvoidwrite endurance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The storage system is segmented into two distinct memory pools: MLC NAND flash for general storage capacity and SLC NAND flash for high-endurance critical data. The controller divides the storage namespace and selectively maps different data types to appropriate memory pools, allowing each segment to serve its optimal function.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different quality levels of storage are applied locally to different data requirements. Critical data requiring high write endurance is stored in SLC memory with superior reliability, while non-critical data is stored in MLC memory for cost-effectiveness. The system applies appropriate storage quality to each data segment based on its endurance requirements.

Inventive Principle:

Principle #3Local quality

2Reliability

If SLC NAND flash is used for high endurance storage, then write endurance and reliability are improved, but cost increases

Engineering Contradiction:

Improvewrite enduranceVSAvoidcost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The storage system is segmented into two distinct memory pools: MLC NAND flash for general storage capacity and SLC NAND flash for high-endurance critical data. The controller divides the storage namespace and selectively maps different data types to appropriate memory pools, allowing each segment to serve its optimal function.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different quality levels of storage are applied locally to different data requirements. Critical data requiring high write endurance is stored in SLC memory with superior reliability, while non-critical data is stored in MLC memory for cost-effectiveness. The system applies appropriate storage quality to each data segment based on its endurance requirements.

Inventive Principle:

Principle #3Local quality

3Duration of action of stationary object

If a hybrid MLC/SLC system is implemented, then lifetime and reliability are extended, but system complexity increases

Engineering Contradiction:

Improvesystem lifetimeVSAvoidsystem complexity

Core Design Contradiction:

Duration of action of stationary objectVSDevice complexity

Solution Approach 1:

The controller automatically monitors data integrity, detects failures, and performs remapping operations without external intervention. The system self-manages the complexity of hybrid memory control through automated integrity testing, failure detection, and data relocation, eliminating the need for manual system management.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The system implements continuous feedback loops where the controller monitors MLC memory integrity, detects failures, and triggers remapping to SLC memory. This feedback mechanism automatically adjusts data placement based on real-time memory health status, managing system complexity through closed-loop control.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20250218508A1Lifetime mixed level non-volatile memory system

Publication Date: 2025.07.03 VERVAIN LLC

AI summary

An apparatus for storing data in a nonvolatile memory includes a controller configured to erase a group of physical memory cells in the nonvolatile memory. The controller is configured to write multiple bits of information to each of a first group of physical memory cells in the nonvolatile memory. The controller is configured to map a logical address range to a physical address range for the first group of physical memory cells in the nonvolatile memory. The controller is configured to determine if the first group of physical memory cells fails a data integrity test. If the first group of physical memory cells fails the data integrity test, the controller writes at least some of the information stored in the first group of physical memory cells to a second group of physical memory cells in the nonvolatile memory. The controller writes a single bit of information per cell in the second group of physical memory cells. The controller is configured to map the logical address range to a second physical address range for the second group of physical memory cells.