Mixed 1T and MT Memory Cell Architecture for Row Hammer Mitigation
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Solution Overview
Problem
As memory components decrease in size, the increased density of memory cells leads to faster data degradation due to 'row hammer' attacks, which can be exacerbated by the need to track access counts, thereby degrading memory performance.
Innovation Solution
The implementation of mixed 1 T and MT memory cell architectures within the same memory array, where MT cells are used for counter memory cells to store access counts, allowing for faster read-modify-write cycles and reduced access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If access count tracking is implemented to monitor row hammer attacks, then memory reliability is improved, but access time increases due to additional write operations
Solution Approach 1:
The patent segments the memory array into two distinct regions: a first region with memory cells configured with a first architecture and a second region with memory cells configured with a second architecture. This segmentation allows different access tracking mechanisms to be applied to different regions, optimizing the balance between reliability and access time for each segment.
Solution Approach 2:
The patent applies different architectural qualities to different regions of the memory array. The first region uses memory cells with a first architecture optimized for certain operations, while the second region uses memory cells with a second architecture optimized for other operations. This local differentiation enables tailored optimization for access tracking in specific regions without compromising overall performance.
2Quantity of substance
If memory cell density is increased to improve storage capacity, then area efficiency is improved, but data degradation rate increases due to row hammer attacks
Solution Approach 1:
The patent divides the high-density memory array into segments with different architectural characteristics. By segmenting the array, the patent can apply different protection mechanisms or access patterns to specific regions that are more susceptible to row hammer attacks, thereby mitigating data degradation while maintaining overall high density.
Solution Approach 2:
The patent employs a composite memory architecture combining different memory cell types or configurations within the same array. This composite structure leverages the strengths of each memory cell type to achieve both high storage capacity and improved resistance to row hammer-induced data degradation.
Data Source
AI summary
Single (1 T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.